K. Osada

发表

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

Yasuhisa Shimazaki, Y. Shinozaki, Shigeru Shimada, 2004, IEEE Journal of Solid-State Circuits.

16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors

K. Ishibashi, E. Ibe, K. Osada, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

H. Ishikuro, N. Irie, K. Niitsu, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration

Tadahiro Kuroda, Hiroki Ishikuro, Kenichi Osada, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low power and reliable SRAM memory cell and array design

Kenichi Osada, Koichiro Ishibashi, K. Ishibashi, 2011 .

Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

K. Ishibashi, S. Ikeda, K. Osada, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

K. Ishibashi, E. Ibe, K. Osada, 2003, IEEE J. Solid State Circuits.

A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations

K. Osada, T. Kawahara, R. Takemura, 2003, IEEE International Electron Devices Meeting 2003.

Dream Chip Project at ASET

Kenichi Osada, Kenichi Takeda, Morihiro Kada, 2015 .

Chip-level TSV Process for Development of 3D System LSIs

Futoshi Furuta, Kazuyuki Hozawa, Kenichi Takeda, 2013 .

The Performance and Density Advantages of 3D FPGA

Tadayuki Matsumura, Kenichi Takeda, Naoto Miyamoto, 2012 .

Measurement method for transient programming current of 1T1R phase-change memory

R. Takemura, M. Terao, M. Moniwa, 2006, 2006 IEEE International Conference on Microelectronic Test Structures.

Action-Intention-Based Grasp Control With Fine Finger-Force Adjustment Using Combined Optical-Mechanical Tactile Sensor

Kenichi Osada, Makoto Saen, Kiyoto Ito, 2014, IEEE Sensors Journal.

Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors

Kenichi Osada, Makoto Saen, Kiyoto Ito, 2012, 2012 IEEE/RSJ International Conference on Intelligent Robots and Systems.

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current

Naoki Kitai, Kenichi Osada, Takayuki Kawahara, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Contactless Liquid-Level Measurement With Frequency-Modulated Millimeter Wave Through Opaque Container

K. Osada, T. Nakagawa, K. Kogo, 2013, IEEE Sensors Journal.

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect

K. Osada, T. Kawahara, K. Yamaguchi, 2004, IEEE Journal of Solid-State Circuits.

Reliable Memory Cell Design for Environmental Radiation-Induced Failures in SRAM

Eishi Ibe, Kenichi Osada, E. Ibe, 2011 .

ISLPED 2011 Symposium Organization

Naehyuck Chang, Yu Wang, Jian-Jia Chen, 2011 .

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

Tadahiro Kuroda, Kenichi Osada, Kiichi Niitsu, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Kenichi Osada, Kenichi Kuroda, Masood Khan, 2001, IEEE J. Solid State Circuits.

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

S. Shimada, K. Kato, M. Yamaoka, 2004, IEEE Journal of Solid-State Circuits.

Reviews and Prospects of Nanoscale SRAMs

K. Osada, K. Osada, 2006, 2006 IEEE International Conference on IC Design and Technology.

Development of a CAD tool for 3D-FPGAs

Tadahiro Ohmi, Kenichi Osada, Naoto Miyamoto, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

K. Ishibashi, M. Yamaoka, K. Osada, 2004, IEEE Journal of Solid-State Circuits.