Jie Deng

发表

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

H. Wong, Jie Deng, 2007, IEEE Transactions on Electron Devices.

Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

H. Wong, Jie Deng, 2007, IEEE Transactions on Electron Devices.

A Biomimetic Carbon Nanotube Synapse Circuit

Aaron K. Friesz, A. Parker, Chongwu Zhou, 2006 .

Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization

H. Wong, G. Wan, T. Krishnamohan, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Printed Carbon Nanotube Thin Film Transistors Based on Perhydropolysilazane-Derived Dielectrics for Low Power Flexible Electronics

Jie Deng, Jianwen Zhao, Xiaoqian Li, 2022, SSRN Electronic Journal.

Modeling Carbon Nanotube Sensors

H. Wong, Jie Deng, K. Ghosh, 2007, IEEE Sensors Journal.

Printed solid state electrolyte carbon nanotube thin film transistors for sub-1 V fully printed flexible CMOS inverters

Jie Deng, Jianwen Zhao, M. Robin, 2021 .

Carbon Nanotube Device Modeling and Circuit Simulation

H.-S. Philip Wong, Jie Deng, Albert Lin, 2009 .

Carbon nanotube transistor compact model for circuit design and performance optimization

H.-S. Philip Wong, Jie Deng, Albert Lin, 2008, JETC.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

Jie Deng, H.-S.P. Wong, H. Wong, 2007, IEEE Transactions on Electron Devices.

Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization

H.-S. Philip Wong, Jie Deng, Gordon C. Wan, 2006, IEEE/ACM International Conference on Computer-Aided Design.

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

Ching-Te Chuang, Keunwoo Kim, Jie Deng, 2007, IEEE Transactions on Electron Devices.

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

Ching-Te Chuang, H.-S. Philip Wong, Keunwoo Kim, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Hai Wei, Jie Zhang, H.-S. Philip Wong, 2011, 2011 International Electron Devices Meeting.

Technology Projection Using Simple Compact Models

H.-S. Philip Wong, Jie Deng, Lan Wei, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Fabrication and electrical properties of printed three-dimensional integrated carbon nanotube PMOS inverters on flexible substrates.

Jie Deng, Jianwen Zhao, Shuangshuang Shao, 2022, Nanoscale.

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier

H.-S. Philip Wong, Jie Deng, Islamshah Amlani, 2006, 2006 International Electron Devices Meeting.

Flexible printed single-walled carbon nanotubes olfactory synaptic transistors with crosslinked poly(4-vinylphenol) as dielectrics

Jie Deng, Jianwen Zhao, Shuangshuang Shao, 2021 .