P. Jacob

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

M. Hussein, C. Kenyon, Z. Ma, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

M. Hussein, C. Kenyon, E. Lee, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

100 nm gate length high performance/low power CMOS transistor structure

J. Kavalieros, C. Kenyon, R. Nagisetty, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

P. Bai, C. Auth, V. Chikarmane, 2002, Digest. International Electron Devices Meeting,.

Intel ® Technology Journal Semiconductor Technology and Manufacturing Integration of Mixed-signal Elements into a High- Performance Digital Cmos Process Transistor Elements for 30nm Physical Gate Length and beyond the Intel Lithography Roadmap Emerging Directions for Packaging Technologies 130nm Log

S. Thompson, P. Jacob, 2002 .