H. Shiga

A CMOS bandgap reference circuit with sub-1-V operation

K. Sakui, S. Atsumi, T. Tanzawa, 1999 .

A CMOS band-gap reference circuit with sub 1 V operation

Hitoshi Shiga, Toru Tanzawa, Koji Sakui, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate

Yan Li, Jun Wan, Feng Pan, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput

T. Kamei, S. Tanaka, Y. Watanabe, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 44 mm/sup 2/ 4-bank 8-word page read 64 Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

H. Watanabe, Y. Takano, S. Atsumi, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

H. Watanabe, S. Yamada, Y. Takano, 2000, IEEE Journal of Solid-State Circuits.

A 113mm2 32Gb 3b/cell NAND flash memory

Hong Ding, Masahide Matsumoto, Hiroaki Nasu, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology

Hong Ding, Takeshi Ogawa, Brian Murphy, 2011, 2011 IEEE International Solid-State Circuits Conference.