A. Sachid

发表

Highly robust nanoscale planar double-gate MOSFET device and SRAM cell immune to gate-misalignment and process variations

D. Sharma, V. Rao, A. Sachid, 2009, 2009 2nd International Workshop on Electron Devices and Semiconductor Technology.

Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

C. Hu, A. Sachid, 2012, IEEE Transactions on Electron Devices.

Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?

D. Sharma, V. Rao, A. Sachid, 2008, 2008 IEEE International Electron Devices Meeting.

Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

O. Faynot, S. Venugopalan, Y. S. Chauhan, 2012, IEEE Electron Device Letters.

Drain current model for nanoscale double-gate MOSFETs

M. Patil, V. Rao, A. Sachid, 2009 .

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

C. Hu, D. Kwon, A. Sachid, 2018, IEEE Electron Device Letters.

MoS2 transistors with 1-nanometer gate lengths

Moon J. Kim, H. Wong, C. Hu, 2016, Science.

Monolithic 3D CMOS Using Layered Semiconductors

C. Hu, A. Javey, A. Sachid, 2016, Advanced materials.

Circuit performance analysis of negative capacitance FinFETs

C. Hu, A. Sachid, S. Salahuddin, 2016, 2016 IEEE Symposium on VLSI Technology.

Field-effect transistors built from all two-dimensional material components.

C. Hu, A. Javey, A. Sachid, 2014, ACS nano.

High-gain monolithic 3D CMOS inverter using layered semiconductors

C. Hu, A. Javey, A. Sachid, 2017 .

Van der Waals heterostructures for tunnel transistors

A. Javey, A. Sachid, D. Kiriya, 2015, 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S).

Field-E ff ect Transistors Built from All Two-DimensionalMaterialComponents

C. Hu, A. Javey, A. Sachid, 2014 .

Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications

C. Hu, A. Sachid, Hsiang-Yun Lin, 2017, IEEE Transactions on Electron Devices.

Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model

C. Hu, A. Sachid, S. Salahuddin, 2017, IEEE Transactions on Electron Devices.

Engineering Negative Differential Resistance in NCFETs for Analog Applications

Chenming Hu, Pragya Kushwaha, Sayeef Salahuddin, 2018, IEEE Transactions on Electron Devices.

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

C. Hu, A. Sachid, S. Salahuddin, 2018, IEEE Transactions on Electron Devices.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

M. A. Karim, O. Faynot, Y. Chauhan, 2012, IEEE Transactions on Electron Devices.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

C. Hu, A. Sachid, S. Salahuddin, 2017, IEEE Transactions on Electron Devices.

Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

D.K. Sharma, D. Sharma, V. Rao, 2008, IEEE Electron Device Letters.

Flicker noise in advanced CMOS technology: Effects of halo implant

Xin Zhang, Ali M. Niknejad, Samuel Martin, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

High-gain inverters based on WSe2 complementary field-effect transistors.

Yuping Zeng, Ali Javey, Angada B Sachid, 2014, ACS nano.

Air stable n-doping of WSe2 by silicon nitride thin films with tunable fixed charge density

Kevin M. Chen, A. Javey, A. Sachid, 2014 .

Compact models of negative-capacitance FinFETs: Lumped and distributed charge models

Chenming Hu, Sayeef Salahuddin, Sourabh Khandelwal, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Asif Islam Khan, Chenming Hu, Sayeef Salahuddin, 2016, IEEE Electron Device Letters.

Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

C. Hu, A. Sachid, S. Salahuddin, 2018, IEEE Transactions on Electron Devices.

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Harald Gossner, Ashish Pal, Angada B Sachid, 2011, IEEE Transactions on Electron Devices.

Negative capacitance enables FinFET and FDSOI scaling to 2 nm node

Vita Pi-Ho Hu, Chenming Hu, Angada B. Sachid, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

BSIM-IMG: A Turnkey compact model for fully depleted technologies

Chenming Hu, C. Hu, Y. Chauhan, 2012, 2012 IEEE International SOI Conference (SOI).

Bulk FinFET With Low- $\kappa $ Spacers for Continued Scaling

C. Hu, A. Sachid, Min-Cheng Chen, 2017, IEEE Transactions on Electron Devices.

FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

C. Hu, A. Sachid, Chun-Chi Chen, 2017, IEEE Electron Device Letters.

A Novel Table-Based Approach for Design of FinFET Circuits

Maryam Shojaei Baghini, Mahesh B. Patil, V. Ramgopal Rao, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes

Chenming Hu, A. B. Sachid, C. Hu, 2012, 2012 IEEE International SOI Conference (SOI).

Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect

Hong Zhou, Chenming Hu, Sayeef Salahuddin, 2018, 2018 IEEE Symposium on VLSI Technology.

FinFET With High- $\kappa $ Spacers for Improved Drive Current

Chenming Hu, Angada B. Sachid, C. Hu, 2016, IEEE Electron Device Letters.

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Yao-Jen Lee, C. Hu, W. Yeh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

2D layered materials: From materials properties to device applications

C. Hu, A. Javey, A. Sachid, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

High-gain inverters based on WSe2 complementary field-effect transistors.

A. Javey, A. Sachid, Yongjing Lin, 2014, ACS nano.

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Chenming Hu, ChiaHua Ho, Yi-Ping Hsieh, 2013, 2013 Symposium on VLSI Technology.

Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

C. Hu, A. Javey, A. Sachid, 2015, IEEE Transactions on Nanotechnology.