S. Watanabe

A 67 GHz fmax Lateral Bipolar Transistor with Co-silicided Base Electrode Structure on Thin Film SOI for RF Analog Applications

H. Ishiuchi, J. Matsunaga, H. Nii, 1999, 29th European Solid-State Device Research Conference.

A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories

S. Shiratake, H. Oodaira, K. Ohuchi, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

An experimental DRAM with a NAND-structured cell

F. Masuoka, S. Shiratake, D. Takashima, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

An 18.5ns 128MB SOI DRAM with a floating body cell

Takashi Ohsawa, Shigeyoshi Watanabe, Takeshi Hamamoto, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A new static memory cell based on reverse base current (RBC) effect of bipolar transistor

K. Ohuchi, F. Masuoka, K. Sakui, 1988, Technical Digest., International Electron Devices Meeting.

The stabilized reference-line (SRL) technique for scaled DRAMs

K. Tsuchida, Y. Ogwaki, M. Ohta, 1989, Symposium 1989 on VLSI Circuits.

A folded capacitor cell (F.C.C.) for future megabit DRAMs

K. Hieda, S. Watanabe, M. Wada, 1984, 1984 International Electron Devices Meeting.