K. Nishimura

AC-Coupled Burst-Mode Transmitter Using Baseline-Wander Common-Mode-Rejection Technique for 10-Gbit/s-Class PON Systems

K. Hara, S. Kimura, H. Nakamura, 2008, Journal of Lightwave Technology.

0.25 /spl mu/m CMOS/SIMOX gate array LSI

K. Nishimura, T. Sakai, H. Inokawa, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

A 10 Gb/s burst-mode CDR IC in 0.13 /spl mu/m CMOS

S. Kimura, K. Nishimura, Y. Ohtomo, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

10.3 Gbit/s burst-mode PIN-TIA module with high sensitivity, wide dynamic range and quick response

Keiji Kishine, Kazuyoshi Nishimura, Shunji Kimura, 2008 .

High-speed circuit technology for 10-Gb/s optical burst-mode transmission

Masafumi Nogawa, Hiroaki Katsurai, Kazuyoshi Nishimura, 2010, 2010 Conference on Optical Fiber Communication (OFC/NFOEC), collocated National Fiber Optic Engineers Conference.

A 10G Burst-Mode PIN-TIA Module with 10-nsec Response for PON Systems

N. Yoshimoto, S. Kimura, S. Nishihara, 2007, LEOS 2007 - IEEE Lasers and Electro-Optics Society Annual Meeting Conference Proceedings.

A 10.3125-Gbit/s SiGe BiCMOS Burst-Mode Clock and Data Recovery Circuit with 160-bit Consecutive Identical Digit Tolerance

Jun Terada, Kazuyoshi Nishimura, Tomoaki Kawamura, 2007 .

A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC

N. Yoshimoto, S. Kimura, J. Terada, 2008, IEEE Journal of Solid-State Circuits.

A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC

Jun Terada, Naoto Yoshimoto, Hiroaki Katsurai, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 10-Gb/s burst-mode limiting amplifier using a two-stage active feedback circuit

Jun Terada, Masafumi Nogawa, Kazuyoshi Nishimura, 2009, 2009 Symposium on VLSI Circuits.

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

Jun Terada, Naoto Yoshimoto, Hiroaki Katsurai, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13/spl mu/m CMOS

T. Kawamura, Y. Ohtomo, M. Togashi, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion

Noboru Ishihara, Kazuyoshi Nishimura, Tomoaki Kawamura, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.