M. Takada

发表

A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme

M. Fukuma, S. Saito, T. Takeuchi, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

A 6 ns 1.5 V 4 Mb BiCMOS SRAM

H. Suzuki, K. Nakamura, K. Takeda, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

Memory LSI reliability

M. Fukuma, H. Furuta, M. Takada, 1993, Proc. IEEE.

A 150 ns, 150 mW, 64K dynamic MOS RAM

T. Wada, M. Takada, S. Matsue, 1978, IEEE Journal of Solid-State Circuits.

A High Performance 0.4μm BiCMOS Technology for 16Mb Fast SRAMs

H. Suzuki, K. Nakamura, T. Yamazaki, 1994, ESSDERC '94: 24th European Solid State Device Research Conference.

A 220 MHz pipelined 16 Mb BiCMOS SRAM with PLL proportional self-timing generator

H. Suzuki, K. Nakamura, T. Kimura, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

A novel sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

Kiyotaka Imai, K. Takeda, Y. Kinoshita, 1994, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

Two-dimensional analysis of writing mechanisms for a taper isolated RAM cell

S. Kurosawa, M. Takada, S. Suzuki, 1985, IEEE Transactions on Electron Devices.

A 5 ns 1 Mb ECL BiCMOS SRAM

K. Nakamura, M. Takada, T. Takeshima, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

Two-dimensional analysis of writing mechanisms for a taper isolated RAM cell

M. Takada, S. Suzuki, K. Terada, 1985 .

FA13.4: A 6ns 4Mb ECL 110 BiCMOS SRAM with LV-TTL Mask Option

Kazuyuki Nakamura, Tohru Yamazaki, M. Takada, 1990 .

PLL timing design techniques for large-scale, high-speed, low-power, and low-cost SRAMs

Kazuyuki Nakamura, Tohru Yamazaki, Hiroshi Yoshida, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

Advanced DMOS Memory Cell using Trench Isolation

S. Kurosawa, M. Takada, T. Ishijima, 1982, 1982 Symposium on VLSI Technology. Digest of Technical Papers.

Design for testability in a 200 MFLOPS vector-pipelined processor (VPP)-ULSI

M. Takada, Yasuhiko Hagihara, H. Yamada, 1992, Proceedings First Asian Test Symposium (ATS `92).

High speed submicron BiCMOS memory

Kazuyuki Nakamura, T. Yamazaki, M. Takada, 1995 .

Study of Automatic Bit Line voltage Swing controller for SRAMs

Hiroshi Yoshida, Kiyotaka Imai, Y. Kinoshita, 1995 .

A 300-MHz 16-b BiCMOS video signal processor

T. Enomoto, Masahiro Nomura, Masakazu Yamashina, 1993 .

A 6 ns 4 Mb ECL I/O BiCMOS SRAM with LV-TTL mask option

T. Yamazaki, M. Takada, H. Suzuki, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator

T. Yamazaki, M. Takada, H. Suzuki, 1994 .

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with p-channel access transistors

Kiyotaka Imai, Hiroshi Yoshida, K. Takeda, 1995 .

A 300 MHz 16 b BiCMOS video signal processor

M. Yamashina, M. Takada, K. Suzuki, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Dummy reversal technique in megabit DRAM

M. Takada, T. Takeshima, M. Yoshida, 1987 .

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

K. Nakamura, T. Yamazaki, M. Takada, 1992 .

A new VLSI memory cell using capacitance coupling

M. Takada, S. Suzuki, T. Ishijima, 1982, 1982 International Electron Devices Meeting.

A new VLSI memory cell using DMOS technology (DMOS cell)

M. Takada, S. Suzuki, K. Terada, 1982, IEEE Transactions on Electron Devices.

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

Kiyotaka Imai, Y. Kinoshita, M. Takada, 1996, IEEE J. Solid State Circuits.

A 30 ns 64 Mb DRAM with built-in self-test and repair function

N. Kasai, M. Takada, A. Tanabe, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with p-channel access transistors

H. Toyoshima, Y. Kinoshita, M. Takada, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.