T. Iwamatsu

发表

6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module

K. Kawahara, S. Hino, K. Sadamatsu, 2017, 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD).

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias

T. Hiramoto, T. Iwamatsu, H. Oda, 2013, 2013 Symposium on VLSI Circuits.

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

T. Iwamatsu, T. Hiramoto, R. Tsuchiya, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Influence of recovery characteristics on switching behavior of SiC MOSFETs

Y. Nakao, T. Iwamatsu, S. Nakata, 2020, Japanese Journal of Applied Physics.

Mechanism of Depletion-Mode TDDB for 4H-SiC MOS Structure

S. Hino, T. Iwamatsu, S. Tomohisa, 2017, IEEE Transactions on Device and Materials Reliability.

Thickness dependent integrity of gate oxide on SOI

S. Maegawa, T. Ipposhi, Y. Inoue, 2003 .

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

Y. Inoue, T. Iwamatsu, H. Oda, 1994 .

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE International Electron Devices Meeting.

Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode

Nobuyuki Sugii, Toshiro Hiramoto, Toshiaki Iwamatsu, 2008 .

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2001 .

An SOI-Based 7.5/spl mu/m-Thick 0.15x0.15mm2 RFID Chip

Y. Ohji, M. Usami, A. Sato, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

T. Iwamatsu, T. Hiramoto, H. Oda, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Evaluation of surface defects on SIMOX and their influences on device characteristics

T. Ipposhi, T. Iwamatsu, T. Tanaka, 2000 .

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

T. Eimori, Y. Inoue, T. Iwamatsu, 1994, IEEE International Solid-State Circuits Conference.

Hall effect mobility in inversion layer of 4H-SiC MOSFETs with a thermally grown gate oxide

T. Iwamatsu, K. Kita, H. Amishiro, 2019, Japanese Journal of Applied Physics.

Channel engineering of 4H-SiC MOSFETs using sulphur as a deep level donor

T. Iwamatsu, K. Kita, H. Amishiro, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Difference of soft error rates in SOI SRAM induced by various high energy ion species

T. Lohner, T. Ohshima, T. Makino, 2012 .

Effect of a body-tie structure fabricated by partial trench isolation on the suppression of floating body effect induced soft errors in SOI SRAM investigated using nuclear probes

T. Ohshima, T. Makino, T. Iwamatsu, 2011 .

Evaluation of soft error rates using nuclear probes in bulk and SOI SRAMs with a technology node of 90 nm

T. Ohshima, T. Iwamatsu, M. Takai, 2010 .

Reliability study of bulk and SOI SRAMs using high energy nuclear probes

S. Maegawa, T. Ipposhi, T. Iwamatsu, 2005 .

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)

Hideto Hidaka, Katsuhiro Suma, Kazuyasu Fujishima, 1996 .

Design consideration of 0.4V-operation SOTB MOSFET for super low power application

T. Iwamatsu, H. Oda, Y. Inoue, 2011, 2011 International Meeting for Future of Electron Devices.

Coulomb-limited mobility in 4H-SiC MOS inversion layer as a function of inversion-carrier average distance from MOS interface

T. Iwamatsu, K. Kita, H. Amishiro, 2020, Japanese Journal of Applied Physics.

Surface defects on SOI wafers and their influence on device characteristics

T. Ipposhi, T. Iwamatsu, H. Yamamoto, 2003 .

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Gate Oxide Instability against a Wide Range of Negative Electric Field Stress of SiC MOSFETs

T. Iwamatsu, N. Miura, M. Noguchi, 2021, International Electron Devices Meeting.

Determination of intrinsic phonon-limited mobility and carrier transport property extraction of 4H-SiC MOSFETs

T. Iwamatsu, S. Yamakawa, K. Kita, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Gate Oxide Instability and Lifetime in SiC MOSFETs under a Wide Range of Positive Electric Field Stress

T. Iwamatsu, H. Amishiro, N. Miura, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Carrier transport properties in inversion layer of Si-face 4H–SiC MOSFET with nitrided oxide

T. Iwamatsu, S. Yamakawa, K. Kita, 2019, Japanese Journal of Applied Physics.

Impact of Embedding Schottky Barrier Diodes into 3.3 kV and 6.5 kV SiC MOSFETs

K. Kawahara, S. Hino, K. Sadamatsu, 2018, Materials Science Forum.

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

Hideto Hidaka, T. Iwamatsu, Takahiro Tsuruda, 1993, Proceedings of IEEE International Electron Devices Meeting.

Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Iwamatsu, Narumi Sakashita, Masahide Inuishi, 1998 .

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

T. Iwamatsu, Yasuo Inoue, N. Tsubouchi, 1995 .