J. Neves

发表

Figures of merit to characterize the importance of on-chip inductance

E. Friedman, Y. Ismail, J. Neves, 1998, DAC.

Equivalent Elmore delay for RLC trees

E. Friedman, Y. Ismail, J. Neves, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

Topological design of clock distribution networks based on non-zero clock skew specifications

E. Friedman, J. Neves, 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.

Inductance Effects in RLC Trees

E. Friedman, Y. Ismail, J. Neves, 1999, Great Lakes Symposium on VLSI.

Figures of merit to characterize the importance of on-chip inductance

E. Friedman, Y. Ismail, J. Neves, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Buffer library selection

José Luis Neves, Stephen T. Quay, J. Neves, 2000, Proceedings 2000 International Conference on Computer Design.

Figures of merit to characterize the importance of on-chip inductance

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Parallelizing post-placement timing optimization

Marios C. Papaefthymiou, José Luis Neves, Jiyoun Kim, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Repeater Insertion in Tree Structured

Eby G. Friedman, Yehea Ismail, Jose L. Neves, 2001 .

Transient power in CMOS gates driving LC transmission lines

Eby G. Friedman, Yehea Ismail, Jose L. Neves, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Power dissipated by CMOS gates driving lossless transmission lines

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Dynamic and short-circuit power of CMOS gates driving lossless transmission lines

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

Exploiting on-chip inductance in high speed clock distribution networks

Eby G. Friedman, Yehea Ismail, Jose L. Neves, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

Repeater insertion in tree structured inductive interconnect

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

Eby G. Friedman, José Luis Neves, E. Friedman, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Signal waveform characterization in RLC trees

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Steiner tree optimization for buffers, blockages, and bays

Sachin S. Sapatnekar, Jiang Hu, José Luis Neves, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..