T. Ernst

发表

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

M. Jurczak, G. Ghibaudo, O. Weber, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

O. Faynot, J. Hartmann, C. Fenouillet-Béranger, 2007, 2007 IEEE International Electron Devices Meeting.

Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

C. Carabasse, O. Faynot, J. Hartmann, 2010, 2010 International Electron Devices Meeting.

Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

O. Weber, C. Fenouillet-Béranger, P. Perreau, 2010, 2010 International Electron Devices Meeting.

Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS

N. Cherkashin, J. Hartmann, O. Weber, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

O. Faynot, G. Ghibaudo, J. Hartmann, 2008, 2008 IEEE International Electron Devices Meeting.

Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight (invited)

Sylvain Barraud, P. Brianceau, T. Magis, 2011 .

Determination of film and surface recombination in thin-film SOI devices using gated-diode technique

Denis Flandre, Sorin Cristoloveanu, Jean-Pierre Colinge, 2004 .

Scalability of MSD memory effect

T. Ernst, S. Cristoloveanu, A. Hubert, 2009, 2009 10th International Conference on Ultimate Integration of Silicon.

Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer

T. Ernst, D. Lafond, T. Baron, 2012 .

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

J. Hartmann, O. Weber, F. Andrieu, 2006, IEEE Transactions on Electron Devices.

Ultimately thin double-gate SOI MOSFETs

T. Ouisse, G. Ghibaudo, T. Ernst, 2003 .

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

M. Mouis, O. Weber, F. Andrieu, 2006, IEEE Transactions on Electron Devices.

VLSI silicon multi-gas analyzer coupling gas chromatography and NEMS detectors

M. Roukes, É. Colinet, T. Ernst, 2011, 2011 International Electron Devices Meeting.

High performance miniaturized NEMS sensors Toward co-integration with CMOS?

É. Colinet, P. Batude, O. Rozeau, 2012, 70th Device Research Conference.

Frequency-addressed NEMS arrays for mass and gas sensing applications

É. Colinet, T. Ernst, C. Dupré, 2013, 2013 Transducers & Eurosensors XXVII: The 17th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS & EUROSENSORS XXVII).

Fully monolithic and ultra-compact NEMS-CMOS self-oscillator based-on single-crystal silicon resonators and low-cost CMOS circuitry

É. Colinet, T. Ernst, J. Arcamone, 2014, 2014 IEEE 27th International Conference on Micro Electro Mechanical Systems (MEMS).

Modeling and design of a fully integrated gas analyzer using a μGC and NEMS sensors

É. Colinet, T. Ernst, C. Dupré, 2014 .

An Etch Stop and Sacrificial Materials Study for 3D NEMS-CMOS Co-Integration

T. Ernst, S. Hentz, J. Arcamone, 2014 .

Nanosystems monolithically integrated with CMOS: emerging applications and technologies

É. Colinet, T. Ernst, C. Dupré, 2014, 2014 IEEE International Electron Devices Meeting.

Large Scale Integration of Silicon Nanomechanical Resonators above Industrial CMOS Wafers

G. Sicard, T. Ernst, S. Hentz, 2016 .

The study of radiation effects in emerging micro and nano electro mechanical systems (M and NEMs)

Jacob L. Jones, peixiong zhao, R. Reed, 2016 .

3D nanowire gate-all-around transistors: Specific integration and electrical features

O. Faynot, S. Deleonibus, Gerard Ghibaudo, 2008 .

Raised source/drain (RSD) for 50nm MOSFETs - effect of epitaxy layer thickness on short channel effects

A. Waite, S. Deleonibus, T. Ernst, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

O. Faynot, G. Ghibaudo, T. Ernst, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Growth and Thermal Stability of SiGe/Si Superlattices on Bulk Si Wafers

J. Hartmann, J. Colonna, T. Ernst, 2008 .

Hydrogen annealing of arrays of planar and vertically stacked Si nanowires

Thomas Ernst, J. Foucher, C. Vizioz, 2007 .

Modeling stress retarded self-limiting oxidation of suspended silicon nanowires for the development of silicon nanowire-based nanodevices

Thomas Ernst, A. Hubert, Marc Respaud, 2011 .

SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

O. Faynot, T. Ernst, S. Cristoloveanu, 2011 .

SiGe channel p-MOSFETs scaling-down

G. Ghibaudo, F. Andrieu, T. Ernst, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides

Gerard Ghibaudo, Thomas Ernst, Carlotta Guiducci, 2003 .

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

O. Faynot, T. Ernst, P. Perreau, 2012, IEEE Electron Device Letters.

Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs

G. Ghibaudo, F. Andrieu, T. Ernst, 2004, IEEE Electron Device Letters.

Influence of source/drain formation process on resistance and effective mobility for scaled multi-channel MOSFET

H. Iwai, N. Vulliet, T. Ernst, 2011 .

Carrier mobility degradation due to high dose implantation in ultrathin unstrained and strained silicon-on-insulator films

O. Faynot, G. Ghibaudo, J. Hartmann, 2007 .

In-depth analysis of 3D Silicon nanowire SONOS memory characteristics by TCAD simulations

G. Reimbold, G. Ghibaudo, T. Ernst, 2010, 2010 IEEE International Memory Workshop.

On the mobility in high-κ/metal gate MOSFETs: Evaluation of the high-κ phonon scattering impact

O. Weber, M. Cassé, S. Deleonibus, 2006 .

Junction technology outlook for sub-28nm FDSOI CMOS

Laurent Grenouillet, Yves Morand, Maud Vinet, 2014, 2014 International Workshop on Junction Technology (IWJT).

New routes and diversifications ofr nanoelectronics by the end of the roadmap and beyond

O. Faynot, M. Vinet, T. Ernst, 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.

SILICON TECHNOLOGIES AND COMPONENTS

C. Scientist, T. Ernst, 2017 .

Electron tomography of gate-all-around nanowire transistors

T. Ernst, K. Tachi, C. Dupré, 2010 .

Narrow-channel effects in LOCOS-isolated SOI MOSFETs with variable thickness

Sorin Cristoloveanu, T. Ernst, Dimitris E. Ioannou, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

LOW FREQUENCY NOISE IN SUB-0.1μmSiGepMOSFETs, CHARACTERISATION AND MODELING

G. Ghibaudo, T. Ernst, K. Romanjek, 2004 .

Program at a glance

T. Ernst, É., K. Tachi, 1972, 2009 International Conference on Intelligent Agent & Multi-Agent Systems.

Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices

C. Morin, J. Hartmann, T. Ernst, 2011 .

Engineering strained silicon on insulator wafers with the Smart CutTM technology

Y. Bogumilowicz, N. Kernevez, Pascal Besson, 2004 .

Characterization of the Gate SiO2 /Channel-Si Interface in Thin-gate SiO2 MOSFETs by Low Frequency Noise and Charge Pumping Techniques

G. Ghibaudo, T. Ernst, A. Szewczyk, 2001, 31st European Solid-State Device Research Conference.

Carrier lifetime extraction in fully-depleted SOI devices

J. Colinge, T. Ernst, S. Cristoloveanu, 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

High C content Si/Si1−yCy heterostructures for n-type metal oxide semiconductor transistors

R. Truche, S. Deleonibus, T. Ernst, 2004 .

Four-dimensional spectral low-loss energy-filtered transmission electron tomography of silicon nanowire-based capacitors

P. Bleuet, T. Ernst, D. Lafond, 2012 .

Integration of Ultra-Low Volume Pneumatic Microfluidics with a Three-Dimensional Electrode Network for On-Chip Biochemical Sensing

C. Guiducci, T. Ernst, S. Barraud, 2021, Micromachines.

Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node

O. Faynot, F. Andrieu, S. Deleonibus, 2007 .

Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires

O. Faynot, G. Ghibaudo, T. Ernst, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

15nm-diameter 3D Stacked Nanowires with optional Independent Gates operation (?FET)

O. Faynot, Christian Arvet, S. Deleonibus, 2008 .

NEMS based on top-down technologies: from stand-alone NEMS to VLSI NEMS & NEMS-CMOS integration

T. Ernst, C. Marcoux, P. Ancey, 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.

Reduced pressure chemical vapor deposition of Si/Si1-yCy heterostructures for n-type metal-oxide-semiconductor transistors

J. Hartmann, S. Deleonibus, T. Ernst, 2002 .

3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS

Thomas Ernst, Pierre-Emmanuel Gaillardon, Perrine Batude, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Ultra-thin body Silicon On Insulator and nanowire transistors for 22nm technology node and below

Claire Fenouillet-Beranger, Sylvain Barraud, Olivier Faynot, 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

Sorin Cristoloveanu, Thomas Ernst, Hiroshi Iwai, 2011, Microelectron. Reliab..

Impact of process variability on a frequency-addressed NEMS array sensor used for gravimetric detection

Sebastien Hentz, Olivier Martin, Thomas Ernst, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

HfO2/Al2O3/InGaAs MOSCAP Structures and InGaAs Plasma Nitridation Elaborated in a 300mm Pilot Line

H. Grampeix, G. Reimbold, M. Vinet, 2015 .

Low-frequency noise in strained SiGe core-shell nanowire p-channel field effect transistors

G. Ghibaudo, T. Ernst, K. Tachi, 2010 .

Performance and design considerations for gate-all-around stacked-NanoWires FETs

O. Rozeau, M. Vinet, F. Andrieu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

O. Faynot, G. Ghibaudo, F. Andrieu, 2006, 2006 International Electron Devices Meeting.

Analog/RF Performance of Multichannel SOI MOSFET

O. Rozeau, T. Ernst, N. Vulliet, 2009, IEEE Transactions on Electron Devices.

Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

F. Andrieu, T. Ernst, Y. Bogumilowicz, 2008 .

A unified short-channel compact model for cylindrical surrounding-gate MOSFET

Olivier Rozeau, Thomas Ernst, M. Reyboz, 2011 .

Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration?

O. Faynot, T. Ernst, C. Dupre, 2008, 2008 IEEE International Electron Devices Meeting.

3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

O. Rozeau, O. Faynot, T. Ernst, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Double SiGe:C diffusion barrier channel 40nm CMOS with improved short-channel performances

A. Toffoli, J. Cluzel, J. Hartmann, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics

T. Ernst, J.-M. Hartmann, S. Deleonibus, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Controlling the Polarity of Silicon Nanowire Transistors

Thomas Ernst, T. Ernst, 2013, Science.

Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors

P. Brianceau, S. Barnola, T. Ernst, 2008 .

Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization

Simon Deleonibus, C. Carabasse, Thomas Ernst, 2008 .

Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications

J. Hartmann, S. Barnola, N. Vulliet, 2008 .

Multigate silicon MOSFETs for 45 nm node and beyond

O. Faynot, Maud Vinet, S. Deleonibus, 2006 .

A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

O. Faynot, T. Ernst, S. Cristoloveanu, 2007, IEEE Transactions on Electron Devices.

Ultimately thin SOI MOSFETs: special characteristics and mechanisms

Sorin Cristoloveanu, Yasuo Takahashi, T. Ernst, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

3D source/drain doping optimization in Multi-Channel MOSFET

O. Faynot, H. Iwai, T. Skotnicki, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

Multi-Channel Field-Effect Transistor (MCFET)—Part I: Electrical Performance and Current Gain Analysis

O. Faynot, T. Ernst, S. Deleonibus, 2009, IEEE Transactions on Electron Devices.

Multiple gate devices: advantages and challenges

O. Faynot, M. Vinet, S. Deleonibus, 2005 .

A nanowire gauge factor extraction method for material comparison and in-line monitoring

Sebastien Hentz, Laurent Duraffourg, Thomas Ernst, 2015, 2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS).

Spectroscopic charge pumping in Si nanowire transistors with a high-κ/metal gate

Thomas Ernst, M. Casse, M. Cassé, 2010 .

Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

F. Andrieu, T. Ernst, S. Deleonibus, 2008, 2008 Symposium on VLSI Technology.

Electron transport in thin SOI, strained-SOI and GeOI MOSFET by Monte-Carlo simulation

T. Ernst, S. Barraud, L. Clavelier, 2005 .

Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

Sorin Cristoloveanu, Thomas Ernst, M. Bawedin, 2009 .

Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture

T. Ernst, S. Cristoloveanu, T. Ernst, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Frequency fluctuations in mono- and polysilicon resonators: A new limit of detection

T. Ernst, S. Hentz, M. Gely, 2017, 2017 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS).