L. Brevard

发表

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

M. Jurczak, G. Ghibaudo, O. Weber, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

O. Faynot, J. Hartmann, C. Fenouillet-Béranger, 2007, 2007 IEEE International Electron Devices Meeting.

Drain current variability and MOSFET parameters correlations in planar FDSOI technology

M. Belleville, G. Ghibaudo, O. Weber, 2011, 2011 International Electron Devices Meeting.

Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster

A. Toffoli, O. Faynot, T. Skotnicki, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

A. Toffoli, J. Cluzel, O. Faynot, 2010, 2010 Symposium on VLSI Technology.

Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

O. Weber, C. Fenouillet-Béranger, P. Perreau, 2010, 2010 International Electron Devices Meeting.

Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

O. Faynot, M. Orlowski, T. Skotnicki, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Lateral coupling and immunity to substrate effect in ΩFET devices

Sorin Cristoloveanu, Simon Deleonibus, Olivier Faynot, 2006 .

SiGe channel p-MOSFETs scaling-down

G. Ghibaudo, F. Andrieu, T. Ernst, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

/spl Omega/FETs transistors with TiN metal gate and HfO/sub 2/ down to 10nm

X. Garros, O. Faynot, M. Vinet, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

G. Ghibaudo, S. Barraud, L. Brevard, 2020, Nanotechnology.

Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

J. Mazurier, O. Faynot, G. Ghibaudo, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Opportunities and challenges brought by 3D-sequential integration

G. Sicard, C. Fenouillet-Béranger, F. Andrieu, 2021, 2021 IEEE International Interconnect Technology Conference (IITC).

Ultra-thin body Silicon On Insulator and nanowire transistors for 22nm technology node and below

Claire Fenouillet-Beranger, Sylvain Barraud, Olivier Faynot, 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

Specificities of linear Si QD arrays integration and characterization

M. Cassé, M. Vinet, L. Brevard, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

A systematic investigation of work function in advanced metal gate-HfO2-SiO2 structures with bevel oxide

Sorin Cristoloveanu, Simon Deleonibus, Hiroshi Iwai, 2007 .

Advances, challenges and opportunities in 3D CMOS sequential integration

J. Mazurier, O. Faynot, P. Batude, 2011, 2011 International Electron Devices Meeting.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

X. Garros, O. Faynot, D. Noblet, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell

O. Faynot, V. Arnal, A. Vandooren, 2007, 2007 IEEE International Electron Devices Meeting.

Double SiGe:C diffusion barrier channel 40nm CMOS with improved short-channel performances

A. Toffoli, J. Cluzel, J. Hartmann, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Work Function Investigation in Advanced Metal Gate-HfO2-SiO2 Systems with Bevel Structures

O. Faynot, H. Iwai, S. Deleonibus, 2006, European Solid-State Device Research Conference.

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

O. Rozeau, O. Faynot, F. Andrieu, 2008, 2008 IEEE International Electron Devices Meeting.

A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

C. Fenouillet-Béranger, F. Andrieu, X. Garros, 2021, IEEE Transactions on Electron Devices.

First demonstration of 3D SRAM through 3D monolithic integration of InGaAs n-FinFETs on FDSOI Si CMOS with inter-layer contacts

M. Vinet, H. Hahn, J. Widiez, 2017, 2017 Symposium on VLSI Technology.

Dual Strained Channel co-integration into CMOS, RO and SRAM cells on FDSOI down to 17nm gate length

O. Faynot, P. Batude, M. Vinet, 2010, 2010 International Electron Devices Meeting.