M. Ercken

发表

Line edge roughness: characterization, modeling and impact on device behavior

W. Sansen, S. Decoutere, J. Croon, 2002, Digest. International Electron Devices Meeting,.

FinFETs and Their Futures

N. Horiguchi, N. Collaert, A. Veloso, 2011 .

Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node

M. H. van der Veen, J. Bekaert, K. Croes, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Spintronic majority gates

A. Thean, C. Adelmann, I. Radu, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Junctionless Array with Ultrathin Poly\TiN Floating Gate and HfAlO Based Intergate Dielectric for Sub-15nm Planar NAND Flash

H. Hody, V. Paraschiv, M. Ercken, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

Invited) Vertical Nanowire FET Integration and Device Aspects

Nadine Collaert, Aaron Thean, Tsvetan Ivanov, 2016 .

Subtractive Etch of Ruthenium for Sub-5nm Interconnect

Christopher J. Wilson, Christoph Adelmann, Monique Ercken, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

Determining the impact of statistical fluctuations on resist line edge roughness

M. Ercken, L. Leunissen, G. Patsis, 2005 .

Study of Solvent Diffusion in Polymeric Materials Using Magnetic Resonance Imaging

P. Adriaensens, J. Gelan, M. Ercken, 1995 .

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

Vincent Wiaux, Rita Rooyackers, Staf Verhaegen, 2004 .

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography

S. Demuynck, E. Van Besien, L. Zhang, 2012, 2012 IEEE International Interconnect Technology Conference.

Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck

K. Devriendt, K. Sankaran, G. Pourtois, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Recent Progress in ArF Lithography for the 100nm Node.

G. Vandenberghe, M. Maenhoudt, I. Pollentier, 2001 .

Fabrication of magnetic tunnel junctions connected through a continuous free layer to enable spin logic devices

Christopher J. Wilson, D. Mocuta, I. Radu, 2017, 1711.03609.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Naoto Horiguchi, Tom Schram, Farid Sebaai, 2018 .

Spectral analysis of line width roughness and its application to immersion lithography

Gian Francesco Lorusso, Peter Leunissen, Nadia Vandenbroeck, 2006 .

Full spectral analysis of line width roughness

M. Ercken, A. Azordegan, L. H. A. Leunissen, 2005, SPIE Advanced Lithography.

Vertical nanowire FET integration and device aspects

B. T. Chan, Z. Tao, E. Rosseel, 2016 .

Variable-threshold resist models for lithography simulation

Anne-Marie Goethals, Kurt G. Ronse, Monique Ercken, 1999, Advanced Lithography.

Dynamic leaching procedure on an immersion interference printer

Monique Ercken, Roel Gronheid, Enrico Tenaglia, 2006, SPIE Advanced Lithography.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Line edge roughness: experimental results related to a two-parameter model

M. Ercken, M. Ercken, L. Leunissen, 2004 .

Use of magnetic resonance imaging to study transport of methanol in poly(methyl methacrylate) at variable temperature

P. Adriaensens, J. Gelan, M. Ercken, 1996 .

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell

Naoto Horiguchi, Anabela Veloso, S. Locorotondo, 2010 .

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

R. Rooyackers, E. Augendre, N. Collaert, 2006, 2006 International Electron Devices Meeting.