H. Oda

发表

Novel locally strained channel technique for high performance 55nm CMOS

T. Eimori, Y. Inoue, K. Ota, 2002, Digest. International Electron Devices Meeting,.

Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2016, IEEE Transactions on Electron Devices.

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias

T. Hiramoto, T. Iwamatsu, H. Oda, 2013, 2013 Symposium on VLSI Circuits.

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

T. Iwamatsu, T. Hiramoto, R. Tsuchiya, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

Y. Inoue, T. Iwamatsu, H. Oda, 1994 .

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE International Electron Devices Meeting.

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

Masahide Inuishi, Y. Akasaka, Katsuhiro Tsukamoto, 1991, International Electron Devices Meeting 1991 [Technical Digest].

The area of safe operation of transistors for switching operation

H. Oda, H. Oda, 1966 .

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

T. Iwamatsu, T. Hiramoto, H. Oda, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications

T. Hiramoto, S. Kamohara, H. Oda, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

H. Hada, N. Banno, T. Sakamoto, 2015 .

Elevated source/drain engineering with smooth surface morphology for ultrathin-SOI CMOS

T. Eimori, S. Maeda, S. Maegawa, 2002, Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT..

Three-Dimensional Visualization Technique for Crystal Defects in High Performance p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Embedded SiGe Source/Drain

H. Oda, T. Yamashita, J. Komori, 2010 .

Difference of soft error rates in SOI SRAM induced by various high energy ion species

T. Lohner, T. Ohshima, T. Makino, 2012 .

Effect of a body-tie structure fabricated by partial trench isolation on the suppression of floating body effect induced soft errors in SOI SRAM investigated using nuclear probes

T. Ohshima, T. Makino, T. Iwamatsu, 2011 .

Design consideration of 0.4V-operation SOTB MOSFET for super low power application

T. Iwamatsu, H. Oda, Y. Inoue, 2011, 2011 International Meeting for Future of Electron Devices.

A Novel Low Leakage-Current Ni SALICIDE Process in nMOSFETs on Si(110) Substrate

K. Asai, H. Oda, T. Okudaira, 2007, 2007 IEEE International Electron Devices Meeting.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Spreading resistance profiling of ultra shallow junction fabricated with low energy as implantation and combination of spike lamp and laser annealing processes using scanning spreading resistance microscopy

H. Oda, M. Takai, F. Wakaya, 2014, 2014 20th International Conference on Ion Implantation Technology (IIT).

Ultra-low power and ultra-low voltage devices and circuits for IoT applications

T. Saraya, T. Hiramoto, S. Kamohara, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

Temperature Coefficient of Threshold Voltage in High-k Metal Gate Transistors with Various TiN and Capping Layer Thicknesses

Y. Inoue, H. Oda, T. Yamashita, 2010 .

Effect of <100> channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate length

S. Shimizu, M. Inuishi, K. Sonoda, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).