G. Samudra

发表

A complementary-I-MOS technology featuring SiGe channel and i-region for enhancement of impact-ionization, breakdown voltage, and performance

G. Lo, Y. Yeo, D. Sylvester, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

A Double-Gate Tunneling Field-Effect Transistor with Silicon-Germanium Source for High-Performance, Low Standby Power, and Low Power Technology Applications

Y. Yeo, D. Sylvester, E. Toh, 2007 .

A Physics-based Compact Model for I-MOS Transistors

Y. Yeo, D. Sylvester, E. Toh, 2007 .

Impact Ionization Nanowire Transistor with Multiple-Gates, Silicon-Germanium Impact Ionization Region, and Sub-5 mV/decade Subtheshold Swing

G. Lo, Y. Yeo, D. Sylvester, 2007, 2007 IEEE International Electron Devices Meeting.

Characterization and Physical Origin of Fast Vth Transient in NBTI of pMOSFETs with SiON Dielectric

Y. Yeo, G. Samudra, C. Shen, 2006, 2006 International Electron Devices Meeting.

Fast and slow dynamic NBTI components in p-MOSFET with SiON dielectric and their impact on device life-time and circuit application

Y. Yeo, G. Samudra, Chunxiang Zhu, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions

Y. Yeo, G. Samudra, N. Balasubramanian, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source

Y. Yeo, D. Sylvester, E. Toh, 2008 .

Device Physics and Characteristics of Graphene Nanoribbon Tunneling FETs

G. Samudra, G. Liang, S. Chin, 2010, IEEE Transactions on Electron Devices.

A Simulation Study of Graphene-Nanoribbon Tunneling FET With Heterojunction Channel

Y. Yeo, G. Samudra, G. Liang, 2010, IEEE Electron Device Letters.

Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices

G. Samudra, K. Rajendran, 2000 .

In Situ Surface Passivation and CMOS-Compatible Palladium–Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs

Ming Zhu, Yee-Chia Yeo, Chih-Hang Tung, 2008, IEEE Electron Device Letters.

Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors

Kah-Wee Ang, King-Jien Chui, Yee-Chia Yeo, 2005 .

Sub-femto-farad capacitance-voltage characteristics of single channel gate-all-around nano wire transistors for electrical characterization of carrier transport

N. Singh, G. Lo, D. Kwong, 2008, 2008 IEEE International Electron Devices Meeting.

Graphene Nanoribbon Tunneling Field-Effect Transistors With a Semiconducting and a Semimetallic Heterojunction Channel

G. Samudra, G. Liang, S. Chin, 2012, IEEE Transactions on Electron Devices.

Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current

Y. Yeo, G. Samudra, G. Han, 2009, IEEE Electron Device Letters.

Effects of Gate Field Plates on the Surface State Related Current Collapse in AlGaN/GaN HEMTs

Yung C. Liang, G. Samudra, Huolin Huang, 2014, IEEE Transactions on Power Electronics.

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon $(\hbox{Si}_{1 - y}\hbox{C}_{y})$ Source and Drain Stressors With High Carbon Content

Y. Yeo, G. Samudra, N. Balasubramanian, 2008, IEEE Transactions on Electron Devices.

Investigation of performance limits of germanium double-gated MOSFETs

D. Kwong, L. Chan, G. Samudra, 2003, IEEE International Electron Devices Meeting 2003.

Fast DNBTI components in p-MOSFET with SiON dielectric

D. Kwong, Y. Yeo, G. Samudra, 2005, IEEE Electron Device Letters.

Electrical Characteristics of Memory Devices With a High- $k$ $\hbox{HfO}_{2}$ Trapping Layer and Dual $\hbox{SiO}_{2}/\hbox{Si}_{3}\hbox{N}_{4}$ Tunneling Layer

Y. Yeo, Gang Zhang, G. Samudra, 2007, IEEE Transactions on Electron Devices.

Modelling of transconductance-to-current ratio (gm/ID) analysis on double-gate SOI MOSFETs

G. Samudra, K. Rajendran, 2000 .

Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction

Y. Yeo, E. Toh, G. Wang, 2007 .

Theoretical calculation and efficient simulations of power semiconductor AlGaN/GaN HEMTs

G. Samudra, Huolin Huang, Y. C. Liang, 2012, 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC).

Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

D. Kwong, Y. Yeo, G. Samudra, 2005, IEEE Electron Device Letters.

120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit

Shuming Xu, Yung C. Liang, Ganesh S. Samudra, 2000 .

Simulation of logarithmic time dependence of hot carrier degradation in PMOSFETs

G. Samudra, C. Ling, B. Seah, 1995 .

Modeling of Stress-Retarded Thermal Oxidation of Nonplanar Silicon Structures for Realization of Nanoscale Devices

Guo-Qiang Lo, Hui Zhao, Dim-Lee Kwong, 2010, IEEE Electron Device Letters.

Self-Consistent SchrÖdinger–Poisson Simulations on Capacitance–Voltage Characteristics of Silicon Nanowire Gate-All-Around MOS Devices With Experimental Comparisons

N. Singh, G. Lo, D. Kwong, 2009, IEEE Transactions on Electron Devices.

Modeling of stress-retarded orientation-dependent oxidation: shape engineering of silicon nanowire channels

N. Singh, G. Lo, D. Kwong, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A Variational Approach to the Two-Dimensional Nonlinear Poisson's Equation for the Modeling of Tunneling Transistors

Chun-Huat Heng, Yee-Chia Yeo, G. Samudra, 2008, IEEE Electron Device Letters.

Measurement and simulation of hot carrier degradation in PMOSFET by gate capacitance

Ganesh S. Samudra, C. H. Ling, G. Samudra, 1995 .

A CMOS Compatible Smart Power Synchronous Rectifier

Yung C. Liang, G. Samudra, N. Balasubramanian, 2006 .

Sub 50nm Strained n-FETs Formed on Silicon-Germanium-on-Insulator Substrates and the Integration of Silicon Source/Drain Stressors

G. Lo, Y. Yeo, E. Toh, 2007 .

Fabrication of Strain Relaxed Silicon-Germanium-on-Insulator (Si 0.35 Ge 0.65 OI) Wafers using Cyclical Thermal Oxidation and Annealing

G. Lo, Y. Yeo, E. Toh, 2007 .

Mechanism of Stress Memorization Technique (SMT) and Method to Maximize Its Effect

A See, A. See, F. Benistant, 2011, IEEE Electron Device Letters.

Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

Hui Zhao, S.C. Rustagi, Yee-Chia Yeo, 2008, IEEE Transactions on Electron Devices.

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Ganesh S. Samudra, S Sreelal, G. Samudra, 2002 .

Practical superjunction MOSFET device performance under given process thermal cycles

Yung C. Liang, Ganesh S. Samudra, G. Samudra, 2004 .

Tunable trench gate power MOSFET: a feasible superjunction device and process technology

G. Samudra, Y.C. Liang, Xin Yang, 2004, 30th Annual Conference of IEEE Industrial Electronics Society, 2004. IECON 2004.

Image formation by use of the geometrical theory of diffraction.

Yihong Wu, T. Milster, G. Samudra, 2004, Journal of the Optical Society of America. A, Optics, image science, and vision.

Carrier Backscattering Characteristics of Strained N-MOSFET Featuring Silicon-Carbon Source/Drain Regions

Kah-Wee Ang, King-Jien Chui, Yee-Chia Yeo, 2006, 2006 European Solid-State Device Research Conference.

Novel Rare-Earth Dielectric Interlayers for Wide NMOS Work-Function Tunability in Ni-FUSI Gates

D. Kwong, Y. Yeo, G. Samudra, 2008, IEEE Transactions on Electron Devices.

Interface dipole mechanism and NMOS Ni-FUSI gate work function engineering using rare-earth metal (RE)-based dielectric interlayers

D. Kwong, Y. Yeo, G. Samudra, 2007, 2007 International Semiconductor Device Research Symposium.

Impact of interfacial dipole on effective work function of nickel fully silicided gate electrodes formed on rare-earth-based dielectric interlayers

D. Kwong, Y. Yeo, G. Samudra, 2007 .

Silicon-Carbon Formed Using Cluster-Carbon Implant and Laser-Induced Epitaxy for Application as Source/Drain Stressors in Strained n-Channel MOSFETs

Y. Yeo, G. Samudra, K. Sekar, 2009 .

Silicon–Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

Y. Yeo, L. Chan, G. Samudra, 2008, IEEE Electron Device Letters.

Contact-Resistance Reduction for Strained n-FinFETs With Silicon–Carbon Source/Drain and Platinum-Based Silicide Contacts Featuring Tellurium Implantation and Segregation

Y. Yeo, B. Liu, G. Samudra, 2011, IEEE Transactions on Electron Devices.

Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With Silicon–Carbon Source/Drain Stressors

Y. Yeo, G. Samudra, K. Ang, 2008, IEEE Electron Device Letters.

Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation

Y. Yeo, L. Chan, G. Samudra, 2008, IEEE Electron Device Letters.

Nickel-Aluminum Alloy Silicides with High Aluminum Content for Contact Resistance Reduction and Integration in n-Channel Field-Effect Transistors

Y. Yeo, D. Chi, G. Samudra, 2008 .

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

Y. Yeo, L. Chan, G. Samudra, 2007, IEEE Electron Device Letters.

High-temperature studies of multiple fluorinated traps within an Al2O3 gate dielectric for E-Mode AlGaN/GaN power MIS-HEMTs

Yung C. Liang, G. Lo, G. Samudra, 2016 .

Effect of Gate Threshold Swings by ALD-Al 2 O 3 / AlGaN Interfacial Traps in GaN Power HEMT with Multiple Fluorinated Gate Dielectric Layers

Yung C. Liang, G. Lo, G. Samudra, 2015 .

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

G. Samudra, E. Li, E. Liu, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

First Principle Study of Si and Ge Band Structure for UTB MOSFETs Applications

D. Kwong, Y. Yeo, L. Chan, 2005, 2005 International Semiconductor Device Research Symposium.

Scaling Parameter Dependent Drain Induced Barrier Lowering Effect in Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

G. Samudra, K. Rajendran, 1999 .

Epitaxial Growth of Single Crystalline Ge Films on GaAs Substrates for CMOS Device Integration

Y. Yeo, G. Samudra, H. Chin, 2008 .

Au-Free Normally-Off AlGaN/GaN-on-Si MIS-HEMTs Using Combined Partially Recessed and Fluorinated Trap-Charge Gate Structures

Yung C. Liang, G. Samudra, Huolin Huang, 2014, IEEE Electron Device Letters.

6.5 V High Threshold Voltage AlGaN/GaN Power Metal-Insulator-Semiconductor High Electron Mobility Transistor Using Multilayer Fluorinated Gate Stack

Yung C. Liang, G. Lo, G. Samudra, 2015, IEEE Electron Device Letters.

High output swing monolithic inverter with E-D mode MIS-HEMTs for GaN power integrated circuits

Yung C. Liang, G. Lo, G. Samudra, 2015, 2015 IEEE 11th International Conference on Power Electronics and Drive Systems.

Realistic Simulations on Reverse Junction Characteristics of SiC and GaN Power Semiconductor Devices

Yung C. Liang, G. Samudra, Guannan Wei, 2012 .

Realistic simulation on reverse characteristics of SiC/GaN p-n junctions for high power semiconductor devices

Yung C. Liang, G. Samudra, Guannan Wei, 2011, 8th International Conference on Power Electronics - ECCE Asia.

Threshold voltage instability in AlGaN/GaN HEMTs

Yung C. Liang, G. Samudra, Ting-Fu Chang, 2015, 2015 IEEE 11th International Conference on Power Electronics and Drive Systems.

Influence of OPC features on the profile of 2D mask patterns

Thomas D Milster, Byoung Il Choi, Ganesh S. Samudra, 2002, SPIE Advanced Lithography.

Simulation of trapping properties of high κ material as the charge storage layer for flash memory application

G. Samudra, W. Yoo, Y. Wang, 2006 .

Self-assembled tungsten nanocrystals in high-k dielectric for nonvolatile memory application

G. Samudra, Sungjoo Lee, N. Balasubramanian, 2005 .

Carrier transport in strained N-channel field effect transistors with channel proximate silicon-carbon source/drain stressors

Y. Yeo, G. Samudra, S. Koh, 2010 .

Long retention and low voltage operation using IrO/sub 2/HfAlO/HfSiO/HfalO gate stack for memory application

D. Kwong, Y. Yeo, G. Samudra, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

High quality silicon-germanium-on-insulator wafers fabricated using cyclical thermal oxidation and annealing

Y. Yeo, E. Toh, G. Wang, 2006 .

Enhancement of memory window in short channel non-volatile memory devices using double layer tungsten nanocrystals

Y. Yeo, G. Samudra, N. Balasubramanian, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Simulation of charge pumping current in hot-carrier degraded p-MOSFET's

G. Samudra, L. See, A. Yip, 1998, ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187).

Yttrium- and Terbium-Based Interlayer on $ \hbox{SiO}_{2}$ and $\hbox{HfO}_{2}$ Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Xin Peng Wang, D. Kwong, Y. Yeo, 2007, IEEE Electron Device Letters.

A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET

Ming Zhu, Yee-Chia Yeo, Tsung-Yang Liow, 2008, IEEE Electron Device Letters.

Superjunction Power LDMOS on Partial SOI Platform

K. Buddharaju, G. Samudra, Y.C. Liang, 2007, Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's.

Impact of Auger recombination parameterisations on predicting silicon wafer solar cell performance

G. Samudra, I. M. Peters, A. Aberle, 2014 .

Numerical analysis of injection level dependent effective lifetime on 125 mm undiffused lifetime samples

G. Samudra, B. Hoex, Z. Hameiri, 2014, 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC).

Progression of Superjunction Power MOSFET Devices

G. Samudra, Y.C. Liang, Yu Chen, 2007, IECON 2007 - 33rd Annual Conference of the IEEE Industrial Electronics Society.

Poly flanked VDMOS (PFVDMOS): a superior technology for superjunction devices

G. Samudra, K. Gan, Y.C. Liang, 2001, 2001 IEEE 32nd Annual Power Electronics Specialists Conference (IEEE Cat. No.01CH37230).

Design of novel normally-off AlGaN/GaN HEMTs with combined gate recess and floating charge structures

G. Samudra, Huolin Huang, Chih-Fang Huang, 2013, 2013 IEEE 10th International Conference on Power Electronics and Drive Systems (PEDS).

Tungsten nanocrystals embedded in high-k materials for memory application

G. Samudra, N. Balasubramanian, L. Bera, 2005 .

Nickel-Silicide:Carbon Contact Technology for N-Channel MOSFETs With Silicon–Carbon Source/Drain

G. Lo, Y. Yeo, D. Chi, 2008, IEEE Electron Device Letters.

Probing the ErSi1.7 Phase Formation by Micro-Raman Spectroscopy

Yee-Chia Yeo, Tsung-Yang Liow, Ganesh S. Samudra, 2007 .

Strained n-Channel Transistors With Silicon Source and Drain Regions and Embedded Silicon/Germanium as Strain-Transfer Structure

Y. Yeo, G. Samudra, N. Balasubramanian, 2007, IEEE Electron Device Letters.

Numerical Simulation of Doping Process by BBr3 Tube Diffusion for Industrial n -Type Silicon Wafer Solar Cells

G. Samudra, I. M. Peters, A. Aberle, 2017, IEEE Journal of Photovoltaics.

Predictive simulation framework for boron diffused p+ layer optimization: Sensitivity analysis of boron tube diffusion process parameters of industrial n-type silicon wafer solar cells

Ganesh S. Samudra, Johnson Wong, Armin G. Aberle, 2019, Solar Energy Materials and Solar Cells.

Numerical Analysis of p+ Emitters Passivated by a PECVD AlOx/SiNx Stack☆

G. Samudra, A. Aberle, B. Hoex, 2013 .

Influence of contact doping on graphene nanoribbon heterojunction tunneling field effect transistors

G. Samudra, G. Liang, S. Chin, 2012 .

A computational study on the device performance of graphene nanoribbon heterojunction tunneling FETs based on bandgap engineering

Y. Yeo, G. Samudra, G. Liang, 2010, 68th Device Research Conference.

N-Channel (110)-Sidewall Strained FinFETs With Silicon–Carbon Source and Drain Stressors and Tensile Capping Layer

Yee-Chia Yeo, Tsung-Yang Liow, N. Balasubramanian, 2007, IEEE Electron Device Letters.

Formation of SiGe nanocrystals in HfO2 using in situ chemical vapor deposition for memory applications

D. Kwong, G. Samudra, Sungjoo Lee, 2004 .

Stress Effects on Stabilizing Antiferroelectric Phase in Multilayer Ceramics

K. Yao, M. S. Mirshekarloo, G. Samudra, 2016 .

Modeling Study of InSb Thin Film For Advanced III-V MOSFET Applications

G. Samudra, D. Kwong, G. Samudra, 2006, 2006 International Electron Devices Meeting.

n-MOSFET With Silicon–Carbon Source/Drain for Enhancement of Carrier Transport

Kah-Wee Ang, King-Jien Chui, Yee-Chia Yeo, 2007, IEEE Transactions on Electron Devices.

A VLSI Design for Implementation of Transform Domain Adaptive Filters

Behrouz Farhang-Boroujeny, Ali Najafi, Ganesh S. Samudra, 1999, VLSI Design.

Simulation of Multiple Gate FinFET Device Gate Capacitance and Performance with Gate Length and Pitch Scaling

S.C. Rustagi, G.S. Samudra, M. Jurczak, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Design of Gradient Oxide-Bypassed Superjunction Power MOSFET Devices

Yu Chen, Y.C. Liang, G.S. Samudra, 2007, IEEE Transactions on Power Electronics.

Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices

Y.C. Liang, G. Samudra, G.S. Samudra, 2001, IEEE Electron Device Letters.

Progressive Development of Superjunction Power MOSFET Devices

Xin Yang, Hanhua Feng, Yu Chen, 2008, IEEE Transactions on Electron Devices.

Electrostatics of Ultimately Thin-Body Tunneling FET Using Graphene Nanoribbon

Y. Yeo, G. Samudra, G. Liang, 2011, IEEE Electron Device Letters.

Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory

Kui Yao, Yang Li, Yong Lian, 2015 .

Shape Effects on the Performance of Si and Ge Nanowire Field-Effect Transistors Based on Size Dependent Bandstructure

G. Samudra, G. Liang, Chee Shin Koong, 2010 .

Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM Technique

N. Singh, G. Lo, D. Kwong, 2009, IEEE Electron Device Letters.

Low Schottky barrier height for silicides on n-type Si (100) by interfacial selenium segregation during silicidation

Y. Yeo, L. Chan, G. Samudra, 2008 .

Strained N-channel FinFETs with High-stress Nickel Silicide-Carbon Contacts and Integration with FUSI Metal Gate Technology

Y. Yeo, G. Samudra, N. Balasubramanian, 2007 .

Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length

G. Lo, Y. Yeo, D. Chi, 2006, 2006 International Electron Devices Meeting.

Achieving Conduction Band-Edge Schottky Barrier Height for Arsenic-Segregated Nickel Aluminide Disilicide and Implementation in FinFETs With Ultra-Narrow Fin Widths

Guo-Qiang Lo, Ming Zhu, Yee-Chia Yeo, 2008, IEEE Electron Device Letters.

Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

Yee-Chia Yeo, Lap Chan, G. Samudra, 2007, IEEE Electron Device Letters.

Strained n-Channel FinFETs Featuring In Situ Doped Silicon – Carbon ( Si 1 − y C y ) Source and Drain Stressors With High Carbon Content

Yee-Chia Yeo, Tsung-Yang Liow, Matthias Bauer, 2009 .

Effectiveness of Aluminum Incorporation in Nickel Silicide and Nickel Germanide Metal Gates for Work Function Reduction

D. Kwong, Y. Yeo, G. Samudra, 2007 .

Contact Technology for Strained nFinFETs With Silicon–Carbon Source/Drain Stressors Featuring Sulfur Implant and Segregation

Y. Yeo, G. Samudra, S. Koh, 2012, IEEE Transactions on Electron Devices.

Schottky barrier height tuning of silicides on p-type Si (100) by aluminum implantation and pulsed excimer laser anneal

Y. Yeo, G. Samudra, T. Henry, 2011 .

P-Channel Tri-Gate FinFETs Featuring $\hbox{Ni}_{1 - y}\hbox{Pt}_{y} \hbox{SiGe}$ Source/Drain Contacts for Enhanced Drive Current Performance

Yee-Chia Yeo, Tsung-Yang Liow, Y. Yeo, 2008, IEEE Electron Device Letters.

Process-Induced Strained P-MOSFET Featuring Nickel-Platinum Silicided Source/Drain

Y. Yeo, D. Chi, G. Samudra, 2006 .

N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide

Guo-Qiang Lo, Yee-Chia Yeo, Tsung-Yang Liow, 2007, IEEE Electron Device Letters.

A simple modelling of device speed in double-gate SOI MOSFETs

Ganesh S. Samudra, K Rajendran, G. Samudra, 2000 .

Two-dimensional numerical simulation of boron diffusion for pyramidally textured silicon

G. Samudra, I. M. Peters, B. Hoex, 2014 .

Novel technique to engineer aluminum profile at nickel-silicide/Silicon:Carbon interface for contact resistance reduction, and integration in strained N-MOSFETs with silicon-carbon stressors

Y. Yeo, G. Samudra, Qian Zhou, 2011, 2011 International Electron Devices Meeting.

Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon–Carbon Source/Drain Regions

Y. Yeo, G. Samudra, N. Balasubramanian, 2007, IEEE Transactions on Electron Devices.

Effect of Ferroelectric Damping on Dynamic Characteristics of Negative Capacitance Ferroelectric MOSFET

Yang Li, Kui Yao, K. Yao, 2016, IEEE Transactions on Electron Devices.

Low voltage high speed SiO/sub 2/AlGaN/AlLaO/sub 3/TaN memory with good retention

C. Chen, A. Chin, C.C. Chi, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Nonvolatile flash memory device using Ge nanocrystals embedded in HfAlO high-/spl kappa/tunneling and control oxides: Device fabrication and electrical performance

G. Samudra, G. Samudra, D. Chan, 2004, IEEE Transactions on Electron Devices.

A new robust non-local algorithm for band-to-band tunneling simulation and its application to Tunnel-FET

G. S. Samudra, Y. Yeo, E. Toh, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications

Yee-Chia Yeo, Ganesh S. Samudra, Eng-Huat Toh, 2008 .

Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization

Yee-Chia Yeo, Ganesh S. Samudra, Eng-Huat Toh, 2007 .

Simulation and design of a germanium L-shaped impact-ionization MOS transistor

Y. Yeo, E. Toh, G. Wang, 2007 .

A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance

Yee-Chia Yeo, Lap Chan, G. Samudra, 2008, IEEE Electron Device Letters.

Strain and Materials Engineering for the I-MOS Transistor With an Elevated Impact-Ionization Region

Guo-Qiang Lo, Yee-Chia Yeo, Lap Chan, 2007, IEEE Transactions on Electron Devices.

Tunable oxide-bypassed trench gate MOSFET: breaking the ideal superjunction MOSFET performance line at equal column width

Y.C. Liang, Yong Liu, G. Samudra, 2003, IEEE Electron Device Letters.

Phenomenon of Drain Current Instability on p-GaN Gate AlGaN/GaN HEMTs

Yung C. Liang, G. Samudra, Ting-Fu Chang, 2015, IEEE Transactions on Electron Devices.

Modelling temperature dependence on AlGaN/GaN power HEMT device characteristics

Yung C. Liang, G. Lo, G. Samudra, 2013 .

Delay and Power Evaluation of Negative Capacitance Ferroelectric MOSFET Based on SPICE Model

Kui Yao, Yang Li, Ganesh S. Samudra, 2017, IEEE Transactions on Electron Devices.

Quantitative analysis and prediction of experimental observations on quasi-static hysteretic metal–ferroelectric–metal–insulator–semiconductor FET and its dynamic behaviour based on Landau theory

Yang Li, Yong Lian, Ganesh S. Samudra, 2015 .

Fabrication of p-MOSFETs on Germanium Epitaxially Grown on Gallium Arsenide Substrate by Chemical Vapor Deposition

Y. Yeo, G. Samudra, H. Chin, 2008 .

N-Channel MOSFETs With Embedded Silicon–Carbon Source/Drain Stressors Formed Using Cluster-Carbon Implant and Excimer-Laser-Induced Solid Phase Epitaxy

Yee-Chia Yeo, K. Sekar, W. Krull, 2008, IEEE Electron Device Letters.

Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors

Y. Yeo, G. Samudra, N. Balasubramanian, 2007 .

Strained SiGeSn formed by Sn implant into SiGe and pulsed laser annealing

G. Lo, Y. Yeo, E. Toh, 2007 .

Incorporation of tin in boron doped silicon for reduced deactivation of boron during post-laser-anneal rapid thermal processing

Y. Yeo, G. Samudra, K. Tan, 2007 .

Modeling study of the impact of surface roughness on silicon and Germanium UTB MOSFETs

G. Samudra, A. Chin, Yee-Chia Yeo, 2005, IEEE Transactions on Electron Devices.

Realistic Simulation of Reverse Characteristics of 411-SiC Power Diode

Yung C. Liang, G. Samudra, Guannan Wei, 2007, 2007 International Conference on Power Engineering, Energy and Electrical Drives.

Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors

Yee-Chia Yeo, Ganesh S. Samudra, Anuj Madan, 2008 .

Modelling and Simulation of Field-effect Surface Passivation of Crystalline Silicon-based Solar Cells

G. Samudra, A. Aberle, B. Hoex, 2012 .

Cointegration of In Situ Doped Silicon–Carbon Source and Silicon–Carbon I-Region in P-Channel Silicon Nanowire Impact-Ionization Transistor

Yee-Chia Yeo, Lap Chan, Eng-Huat Toh, 2008, IEEE Electron Device Letters.

Modification of Molybdenum Gate Electrode Work Function via (La-, Al-Induced) Dipole Effect at High-$k/\hbox{SiO}_{2}$ Interface

Dim-Lee Kwong, Yee-Chia Yeo, D. Kwong, 2008, IEEE Electron Device Letters.

Metal-Gate Work Function Modulation Using Hafnium Alloys Obtained by the Interdiffusion of Thin Metallic Layers

Xin Peng Wang, D. Kwong, Y. Yeo, 2007 .

Fast $V_{\rm th}$ Instability in $\hbox{HfO}_{2}$ Gate Dielectric MOSFETs and Its Impact on Digital Circuits

Dim-Lee Kwong, Tian Yang, Xinpeng Wang, 2006, IEEE Transactions on Electron Devices.

Fast Vth instability in HfO2 gate dielectric MOSFETs and Its impact on digital circuits

S. C. Rustagit, D. Kwong, Y. Yeo, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

High‐field electron transport for ellipsoidal multivalley band structure of silicon

V. Arora, G. Samudra, S. Chua, 1992 .

n-Channel GaAs MOSFET with TaN ∕ HfAlO Gate Stack Formed Using In Situ Vacuum Anneal and Silane Passivation

Y. Yeo, G. Samudra, H. Chin, 2008 .

Power Microelectronics: Device and Process Technologies

Yung C. Liang, G. Samudra, 2008 .

Strained p-Channel FinFETs With Extended $\Pi$ -Shaped Silicon–Germanium Source and Drain Stressors

Yee-Chia Yeo, Tsung-Yang Liow, N. Balasubramanian, 2007, IEEE Electron Device Letters.

Strain enhancement in spacerless N-channel FinFETs with silicon-carbon source and drain stressors

Y. Yeo, G. Samudra, N. Balasubramanian, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Drive-Current Enhancement in FinFETs Using Gate-Induced Stress

Yee-Chia Yeo, Tsung-Yang Liow, Chih-Hang Tung, 2006, IEEE Electron Device Letters.

Spacer Removal Technique for Boosting Strain in n-Channel FinFETs With Silicon-Carbon Source and Drain Stressors

Ming Zhu, Yee-Chia Yeo, Tsung-Yang Liow, 2008, IEEE Electron Device Letters.