Natesan Venkateswaran

Optimization objectives and models of variation for statistical gate sizing

Dennis Sylvester, Vladimir Zolotov, Richard B. Brown, 2005, ACM Great Lakes Symposium on VLSI.

A constructive method for data path area estimation during high-level VLSI synthesis

Dinesh Bhatia, Ranga Vemuri, Anurag Gupta, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

First-Order Incremental Block-Based Statistical Timing Analysis

K. Ravindran, Jeffrey G. Hemmett, Chandramouli Visweswariah, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A distributed timing analysis framework for large designs

Martin D. F. Wong, Tsung-Wei Huang, Natesan Venkateswaran, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

First-order incremental block-based statistical timing analysis

Jeffrey G. Hemmett, Natesan Venkateswaran, D. Beece, 2004, Proceedings. 41st Design Automation Conference, 2004..

First-Order Incremental Block-Based Statistical Timing Analysis

Jeffrey G. Hemmett, Natesan Venkateswaran, D. Beece, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.