C. Visweswariah

发表

D. J. Hathaway, P. Strenski, Xiaoliang Bai, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Statistical timing for parametric yield prediction of digital integrated circuits

R. Otten, C. Visweswariah, J. Jess, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Optimization techniques for high-performance digital circuits

Chandramouli Visweswariah, C. Visweswariah, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Gradient-based optimization of custom circuits using a static-timing formulation

C. B. Whan, A. Conn, P. Strenski, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

Optimization techniques for high-performance digital circuits

C. Visweswariah, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Optimization of custom MOS circuits by transistor sizing

Gregory L. Morrill, A. Conn, C. Visweswariah, 1996, Proceedings of International Conference on Computer Aided Design.

Electronic Circuit and System Simulation Methods

Ronald A. Rohrer, Chandramouli Visweswariah, L. T. Pillage, 1994 .

JiffyTune: circuit optimization using time-domain sensitivities

Andrew R. Conn, Chai Wah Wu, Ruud A. Haring, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Circuit optimization via adjoint Lagrangians

A. Conn, C. Wu, C. Visweswariah, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Incremental Event-Driven Simulation of Digital FET Circuits

Chandramouli Visweswariah, Jalal A. Wehbeh, C. Visweswariah, 1993, 30th ACM/IEEE Design Automation Conference.

Inaccuracies in power estimation during logic synthesis

Daniel Brand, Chandramouli Visweswariah, D. Brand, 1996, Proceedings of International Conference on Computer Aided Design.

Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation

Andrew R. Conn, Chandramouli Visweswariah, A. Conn, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

First-Order Incremental Block-Based Statistical Timing Analysis

K. Ravindran, Jeffrey G. Hemmett, Chandramouli Visweswariah, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

Chandramouli Visweswariah, Ralph H. J. M. Otten, Jochen A. G. Jess, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Noise considerations in circuit optimization

Chandu Visweswariah, A. Conn, C. Visweswariah, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).