S. Kulkarni

High Performance Level Conversion for Dual Design

Dennis Sylvester, Sarvesh H. Kulkarni, D. Sylvester, 2004 .

Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias

David Blaauw, Dennis Sylvester, Sarvesh H. Kulkarni, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

Pramod Kolar, Uddalak Bhattacharya, Fatih Hamzaoglu, 2008, IEEE Journal of Solid-State Circuits.

Pushing ASIC performance in a power envelope

Dennis Sylvester, John M. Cohn, David Z. Pan, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

A new algorithm for improved VDD assignment in low power dual VDD systems

Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell

Zhanping Chen, Sangwoo Pae, W. Hafez, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High-density 3-D metal-fuse PROM featuring 1.37µm2 1T1R bit cell in 32nm high-k metal-gate CMOS technology

Lei Jiang, Zhanping Chen, Kevin Zhang, 2009, 2009 Symposium on VLSI Circuits.