D. Somasekhar

发表

Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson, K. Roy, M. Johnson, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays

K. Roy, J. Tschanz, V. De, 2010, 2010 International Electron Devices Meeting.

Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson, Kaushik Roy, Dinesh Somasekhar, 1999, DAC '99.

A model for leakage control by MOS transistlor stacking

Mark C. Johnson, K. Roy, D. Somasekhar, 1997 .

An energy recovery static RAM memory core

Kaushik Roy, Yibin Ye, Dinesh Somasekhar, 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Mircea R. Stan, Sriram R. Vangal, Vasantha Erraguntla, 2002 .

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration

Shekhar Y. Borkar, Tanay Karnik, Dinesh Somasekhar, 2011, IET Comput. Digit. Tech..

Reducing cache power with low-cost, multi-bit error-correcting codes

Wei Wu, Alaa R. Alameldeen, Chris Wilkerson, 2010, ISCA.

Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances

Arijit Raychowdhury, Tanay Karnik, Dinesh Somasekhar, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Fine-Grained Redundancy in Adders

Kaushik Roy, Patrick Ndai, Shih-Lien Lu, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances

J. Tschanz, V. De, K. Roy, 2011, IEEE Transactions on Electron Devices.

Models and algorithms for bounds on leakage in CMOS circuits

Mark C. Johnson, Kaushik Roy, Dinesh Somasekhar, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

J. Tschanz, S. Narendra, V. De, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

James Tschanz, Arijit Raychowdhury, Dinesh Somasekhar, 2014, IEEE Journal of Solid-State Circuits.

A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique

M. Khellah, V. De, Yibin Ye, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

J. Tschanz, S. Narendra, R. Krishnamurthy, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

I/sub DD/ waveforms analysis for testing of domino and low voltage static CMOS circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

The Applicability of IDD Waveform Analysis to Testing of CMOS Circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1997 .