Andrzej Hlawiczka

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Analysis of operation of ring LFSR used for testing of unidirectional interleaved interconnections

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2011, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011.

Interconnect Faults Identification and Localization Using Modified Ring LFSRs

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Comments on "Procedures for Eliminating Static and Dynamic-Hazards in Test Generation"

Andrzej Hlawiczka, 1978, IEEE Trans. Computers.

Proceedings of the Second European Dependable Computing Conference on Dependable Computing

João Gabriel Silva, Andrzej Hlawiczka, Luca Simoncini, 1996 .

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Dependable Computing - EDCC-2: Second European Dependable Computing Conference, Taormina, Italy, October 2 - 4, 1996. Proceedings

João Gabriel Silva, Andrzej Hlawiczka, Luca Simoncini, 1996 .

Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer

Andrzej Hlawiczka, 1984, Fehlertolerierende Rechensysteme.

Test Pattern Generator for Delay Faults

Andrzej Hlawiczka, Tomasz Rudnicki, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR

Andrzej Hlawiczka, 1989, Fehlertolerierende Rechensysteme.

Testing of interconnections with use of reduced-size signature-based diagnostic dictionary

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

Test-per-Clock Detection, Localization and Identification of Interconnect Faults

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2006, Eleventh IEEE European Test Symposium (ETS'06).

A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits

Tomasz Garbolino, Andrzej Hlawiczka, 1999, EDCC.

Dependable Computing — EDCC-2

João Gabriel Silva, Andrzej Hlawiczka, Luca Simoncini, 1996, Lecture Notes in Computer Science.

A linear code-preserving signature analyzer COPMISR

Michael Gössel, Egor S. Sogomonyan, Andrzej Hlawiczka, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata

Andrzej Hlawiczka, Michal Kopec, 2000, Proceedings of the Ninth Asian Test Symposium.

Universal Test Controller Chip for Board Self Test

Andrzej Hlawiczka, Dariusz Badura, 1987, Fehlertolerierende Rechensysteme.

Testing of crosstalk-type dynamic faults in interconnection networks with use of Ring LFSRs

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

Effective BIST for crosstalk faults in interconnects

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer

Andrzej Hlawiczka, 1986, IEEE Transactions on Computers.

Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks

Andrzej Hlawiczka, 1992, IEEE Trans. Computers.

Low cost BIST for EDAC circuits

Andrzej Hlawiczka, Dariusz Badura, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Reduced-size signature-based diagnostic dictionary for interconnection testing

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2010, PDeS.

Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures

Andrzej Hlawiczka, Jacek Binda, 1994, FPL.

Efficient test pattern generators based on specific cellular automata structures

Tomasz Garbolino, Andrzej Hlawiczka, 2002, Microelectron. Reliab..