N. Patil

发表

Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes

H. Wong, S. Mitra, Chongwu Zhou, 2009, IEEE Transactions on Nanotechnology.

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits

H. Wong, S. Mitra, N. Patil, 2009, IEEE Transactions on Nanotechnology.

COMPOSITE POLYSILICON-PLATINUM LATERAL NANOELECTROMECHANICAL RELAYS

R. Howe, H. Wong, S. Mitra, 2010 .

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors

Hai Wei, Nishant Patil, Subhasish Mitra, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures

H. Wong, S. Mitra, N. Patil, 2008, 2008 Symposium on VLSI Technology.

A metallic-CNT-tolerant carbon nanotube technology using Asymmetrically-Correlated CNTs (ACCNT)

Hai Wei, S. Mitra, N. Patil, 2006, 2009 Symposium on VLSI Technology.

Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits

Hai Wei, Jie Zhang, Subhasish Mitra, 2010, 2010 Symposium on VLSI Technology.

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Imperfection-Immune Carbon Nanotube VLSI Circuits

H. Wong, S. Mitra, N. Patil, 2011 .

Advancements with carbon nanotube digital systems

H. Wong, S. Mitra, N. Patil, 2014, IEEE International Interconnect Technology Conference.

CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

Subhasish Mitra, Albert Lin, Chongwu Zhou, 2009, Nano letters.

Efficient FPGAs using nanoelectromechanical relays

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2010, FPGA '10.

Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks.

Zhenan Bao, Subhasish Mitra, Nishant Patil, 2012, ACS nano.

Selective dispersion of high purity semiconducting single-walled carbon nanotubes with regioregular poly(3-alkylthiophene)s.

Zhenan Bao, Francois Gygi, Giulia Galli, 2011, Nature communications.

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Carbon Nanotube Robust Digital VLSI

Hai Wei, H.-S. Philip Wong, Lan Wei, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines

Hai Wei, Jie Zhang, H.-S Philip Wong, 2010, IEEE Transactions on Electron Devices.

Robust System Design

Jie Zhang, David Lin, Subhasish Mitra, 2010, 2010 23rd International Conference on VLSI Design.

High performance germanium n-MOSFET with antimony dopant activation beyond 1×1020 cm−3

Y. Nishi, R. Brennan, S.-L. Cheng, 2010, 2010 International Electron Devices Meeting.

The effect of amine protonation on the electrical properties of spin-assembled single-walled carbon nanotube networks

S. Mitra, Zhenan Bao, N. Patil, 2011, Nanotechnology.

Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis

Hai Wei, Subhasish Mitra, Albert Lin, 2011 .

Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits

Nishant Patil, Subhasish Mitra, Jie Zhang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Overcoming carbon nanotube variations through co-optimized technology and circuit design

Jie Zhang, Subhasish Mitra, Nishant Patil, 2011, 2011 International Electron Devices Meeting.

Solution assembly of organized carbon nanotube networks for thin-film transistors.

S. Mitra, S. Barman, Zhenan Bao, 2009, ACS nano.

Linear increases in carbon nanotube density through multiple transfer technique.

Hai Wei, Subhasish Mitra, Hong-Yu Chen, 2011, Nano letters.

Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement

Giovanni De Micheli, H.-S. Philip Wong, Nishant Patil, 2010, Design Automation Conference.

VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs

Hai Wei, Jie Zhang, Subhasish Mitra, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration

Hai Wei, H.-S.P. Wong, S. Mitra, 2009, IEEE Transactions on Electron Devices.

Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes

H.-S. Philip Wong, Subhasish Mitra, Albert Lin, 2008 .

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Hai Wei, Jie Zhang, H.-S. Philip Wong, 2011, 2011 International Electron Devices Meeting.

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits

Nishant Patil, Subhasish Mitra, Jie Zhang, 2008, 2008 Design, Automation and Test in Europe.

Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs

S. Mitra, N. Patil, H. Wong, 2009, IEEE Transactions on Nanotechnology.

Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes

Hai Wei, J. Zhang, S. Mitra, 2011, IEEE Transactions on Nanotechnology.

Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Carbon nanotube circuits: Living with imperfections and variations

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

58.4: Invited Paper: Solution Assembly of Transistor Arrays Based on Sorted Nanotube Networks for Large‐Scale Flexible Electronic Applications

S. Mitra, Zhenan Bao, M. Roberts, 2009 .

Selective dispersion of high purity semiconducting single-walled carbon nanotubes with regioregular poly(3-alkylthiophene)s.

F. Gygi, H. Lee, N. Patil, 2011, Nature communications.

Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks.

H. Wong, S. Mitra, Zhenan Bao, 2012, ACS nano.

Surface Science of Catalyst Dynamics for Aligned Carbon Nanotube Synthesis on a Full-Scale Quartz Wafer

H. Wong, Y. Nishi, D. Akinwande, 2009 .