A. Lin

发表

Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes

H. Wong, S. Mitra, Chongwu Zhou, 2009, IEEE Transactions on Nanotechnology.

Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures

H. Wong, S. Mitra, N. Patil, 2008, 2008 Symposium on VLSI Technology.

A metallic-CNT-tolerant carbon nanotube technology using Asymmetrically-Correlated CNTs (ACCNT)

Hai Wei, S. Mitra, N. Patil, 2006, 2009 Symposium on VLSI Technology.

Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits

Hai Wei, Jie Zhang, Subhasish Mitra, 2010, 2010 Symposium on VLSI Technology.

Current Scaling in Aligned Carbon Nanotube Array Transistors With Local Bottom Gating

Albert Lin, Zhihong Chen, H. Wong, 2010, IEEE Electron Device Letters.

Imperfection-Immune Carbon Nanotube VLSI Circuits

H. Wong, S. Mitra, N. Patil, 2011 .

Phase II trial of preoperative 3D conformal radiotherapy, protracted venous infusion 5-fluorouracil, and weekly CPT-11, followed by surgery for ultrasound-staged T3 rectal cancer.

A. Koong, A. Lin, J. Poen, 2003, International journal of radiation oncology, biology, physics.

CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

Subhasish Mitra, Albert Lin, Chongwu Zhou, 2009, Nano letters.

Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Increasing the semiconducting fraction in ensembles of single-walled carbon nanotubes

H.-S. Philip Wong, Albert Lin, Hong-Yu Chen, 2012 .

Carbon Nanotube Robust Digital VLSI

Hai Wei, H.-S. Philip Wong, Lan Wei, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines

Hai Wei, Jie Zhang, H.-S Philip Wong, 2010, IEEE Transactions on Electron Devices.

Carbon Nanotube Device Modeling and Circuit Simulation

H.-S. Philip Wong, Jie Deng, Albert Lin, 2009 .

Carbon nanotube transistor compact model for circuit design and performance optimization

H.-S. Philip Wong, Jie Deng, Albert Lin, 2008, JETC.

Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis

Hai Wei, Subhasish Mitra, Albert Lin, 2011 .

Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement

Giovanni De Micheli, H.-S. Philip Wong, Nishant Patil, 2010, Design Automation Conference.

VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs

Hai Wei, Jie Zhang, Subhasish Mitra, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration

Hai Wei, H.-S.P. Wong, S. Mitra, 2009, IEEE Transactions on Electron Devices.

Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes

H.-S. Philip Wong, Subhasish Mitra, Albert Lin, 2008 .

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Hai Wei, Jie Zhang, H.-S. Philip Wong, 2011, 2011 International Electron Devices Meeting.

Technology Projection Using Simple Compact Models

H.-S. Philip Wong, Jie Deng, Lan Wei, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs

S. Mitra, N. Patil, H. Wong, 2009, IEEE Transactions on Nanotechnology.

Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes

Hai Wei, J. Zhang, S. Mitra, 2011, IEEE Transactions on Nanotechnology.

Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Carbon nanotube circuits: Living with imperfections and variations

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Surface Science of Catalyst Dynamics for Aligned Carbon Nanotube Synthesis on a Full-Scale Quartz Wafer

H. Wong, Y. Nishi, D. Akinwande, 2009 .