S. Inaba

发表

FinFET Process and Integration Technology for High Performance LSI in 22 nm node and beyond

Y. Tsunashima, H. Kawasaki, A. Yagishita, 2007, 2007 International Workshop on Junction Technology.

Origin of “current-onset voltage” variability in scaled MOSFETs

T. Hiramoto, S. Inaba, T. Mizutani, 2010, 2010 Silicon Nanoelectronics Workshop.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE

T. Kudo, H. Ishiuchi, M. Takayanagi, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Analyses of 5σ Vth fluctuation in 65nm-MOSFETs using takeuchi plot

K. Takeuchi, T. Hiramoto, S. Inaba, 2008, 2008 Symposium on VLSI Technology.

Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics

Y. Tsunashima, T. Yamamoto, H. Ishiuchi, 2002, Digest. International Electron Devices Meeting,.

Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs

A. Kumar, T. Hiramoto, K. Takeuchi, 2010, 2010 IEEE International SOI Conference (SOI).

Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET

T. Ohguro, K. Okano, T. Izumida, 2009, 2009 European Microwave Integrated Circuits Conference (EuMIC).

Threshold voltage roll-up/roll-off characteristic control in sub-0.2-/spl mu/m single workfunction gate CMOS for high-performance DRAM applications

R. Katsumata, G. Bronner, K. Sunouchi, 2002 .

The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generation

Y. Toyoshima, N. Kusunoki, S. Kawanaka, 2006, 2009 Symposium on VLSI Technology.

Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method

Tohru Mogami, Akio Nishida, Toshiro Hiramoto, 2010 .

High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method

K. Takeuchi, T. Hiramoto, S. Inaba, 2011 .

Error evaluation of C-V characteristic measurements in ultra-thin gate dielectrics

K. Ishimaru, S. Inaba, H. Suto, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

Thermal-Annealing Effects on Dopant Redistribution in Nanoscale Si Fin

K. Okano, T. Izumida, T. Kanemura, 2011 .

Advantage of Plasma Doping for Source/Drain Extension in Bulk Fin Field Effect Transistor

Takashi Izumida, Satoshi Inaba, K. Okano, 2011 .

Statistic characteristics of “current-onset voltage” in scaled MOSFETs analyzed by 8k DMA TEG

A. Kumar, S. Kamohara, A. Nishida, 2010, 2010 Silicon Nanoelectronics Workshop.

Contact resistance reduction of Pt-incorporated NiSi for continuous CMOS scaling ∼ Atomic level analysis of Pt/B/As distribution within silicide films ∼

S. Kawanaka, S. Inaba, Y. Toyoshima, 2008, 2008 IEEE International Electron Devices Meeting.

Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation

S. Kawanaka, S. Inaba, Y. Toyoshima, 2011, IEEE Transactions on Electron Devices.

The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET

T. Ohguro, Y. Toyoshima, S. Inaba, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-/spl mu/m pMOSFET's

S. Inaba, Y. Toyoshima, A. Murakoshi, 1999 .

Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG

T. Hiramoto, K. Takeuchi, S. Inaba, 2010, 2010 International Electron Devices Meeting.

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

Y. Tsunashima, K. Yahashi, K. Matsuo, 2006, 2006 International Electron Devices Meeting.

3D Flash Memory for Data-Intensive Applications

Satoshi Inaba, S. Inaba, 2018, International Memory Workshop.

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Improvement ofDriveCurrent inBulk-FinFET using Full3D Process/DeviceSimulations

H. Kawasaki, A. Yagishita, K. Ishimaru, 2006 .