H. Onodera

发表

Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation

T. Matsumoto, K. Kobayashi, H. Onodera, 2012, 2012 International Electron Devices Meeting.

A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI

J. Furuta, H. Onodera, M. Masuda, 2014, IEEE Transactions on Nuclear Science.

Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization

H. Onodera, S. Fujimoto, A. Islam, 2013, IEEE Transactions on Semiconductor Manufacturing.

On-chip metamaterial transmission-line based on stacked split-ring resonator for millimeter-wave LSIs

H. Onodera, A. Tsuchiya, 2009, 2009 Asia Pacific Microwave Conference.

Step by step placement strategies for building block layout

H. Onodera, Mamoru Sakamoto, T. Kurihara, 1989, IEEE International Symposium on Circuits and Systems,.

A 65 nm Complementary Metal--Oxide--Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit

H. Onodera, Kazutoshi Kobayashi, H. Makino, 2011 .

Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing

Kazutoshi Kobayashi, Hidetoshi Onodera, Hiroaki Makino, 2012 .

An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted N-channel MOSFET's

H. Onodera, H. Onodera, M. Nishida, 1981, IEEE Transactions on Electron Devices.

Measurement of temperature effect on random telegraph noise induced delay fluctuation

H. Onodera, A. Islam, Masashi Oka, 2018, 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS).

A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones

Hidetoshi Onodera, Kosuke Takai, Xiang Li, 2001 .

Light intensity modulation based on guided-to-radiation mode coupling in heterostructure waveguides.

I. Awai, H. Onodera, M. Nakajima, 1984, Applied optics.

A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis

H. Onodera, M. Hashimoto, 2000 .

An Optical Parallel Multiplier Using Nanophotonic Analog Adders and Optoelectronic Analog-to-Digital Converters

T. Ishihara, H. Onodera, M. Notomi, 2018, 2018 Conference on Lasers and Electro-Optics (CLEO).

Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning

H. Onodera, A. Islam, Misaki Udo, 2020, 2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS).

Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation

T. Matsumoto, H. Onodera, Kazutoshi Kobayashi, 2012 .

Variability Characterization Using an RO-array Test Structure and Its Impact on Design

Kazutoshi Kobayashi, Hidetoshi Onodera, Shinichi Nishizawa, 2010 .

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing

Hidetoshi Onodera, Tohru Ishihara, Jun Shiomi, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Statistical Gate-Delay Model Considering Intra-Gate Variability

Hidetoshi Onodera, Ken-ichi Okada, Kento Yamaoka, 2003, ICCAD.

Variable RF Inductor on Si CMOS Chip

Kenichi Okada, Hidetoshi Onodera, Kazuya Masu, 2003 .

Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)

Kenichi Okada, Hidetoshi Onodera, Keikichi Tamaru, 1999 .

Special Issue on Development of Advanced Computer Systems

Hiroshi Nakashima, Taisuke Boku, Hidetoshi Onodera, 2003 .

A method for improving reusability of design procedures of analog circuits—storage and reuse of design constraints and uncertain parameters

Hidetoshi Onodera, Takashi Morie, Keikichi Tamaru, 2000 .

Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation

N. Banno, T. Sakamoto, H. Ochi, 2022 .

Refractive-index measurement of bulk materials: prism coupling method.

I. Awai, H. Onodera, J. Ikenoue, 1983, Applied optics.

Title Analytical Stability Modeling for CMOS Latches in Low Voltage Operation

T. Ishihara, H. Onodera, Tatsuya KAMAKAR1t•a, 2020 .

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics

T. Ishihara, H. Onodera, M. Notomi, 2020, 2020 International Conference on Rebooting Computing (ICRC).

Analysis of graded-index fibers by means of the transverse resonance method

I. Awai, H. Onodera, N. Shibanuma, 1982 .

Impact of anomalous skin effect on metal wire for terahertz integrated circuit

H. Onodera, A. Tsuchiya, 2015, 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

A statistical gate delay model for intra-chip and inter-chip variabilities

H. Onodera, K. Okada, K. Yamaoka, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

Return path selection for loop RL extraction

Masanori Hashimoto, Hidetoshi Onodera, Akira Tsuchiya, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Timing analysis considering temporal supply voltage fluctuation

Masanori Hashimoto, Hidetoshi Onodera, Takashi Sato, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Equivalent waveform propagation for static timing analysis

Masanori Hashimoto, Hidetoshi Onodera, Yuji Yamada, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Analytic Crosstalk Noise Model Considering Coupling Location : Application to Practical Circuits

Masanori Hashimoto, Hidetoshi Onodera, Masao Takahashi, 2001 .

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion

Masanori Hashimoto, Hidetoshi Onodera, Takashi Sato, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation

Takashi Morie, Hidetoshi Onodera, Keikichi Tamaru, 1995 .

Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits

T. Ishihara, H. Onodera, Jun Shiomi, 2022, 2022 IEEE 35th International System-on-Chip Conference (SOCC).

A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias

H. Onodera, Jun Shiomi, Kentaro Nagai, 2020, 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

High-efficiency light modulator using guided-to-radiation mode coupling in a graded-index waveguide.

H. Onodera, M. Nakajima, 1986, Applied optics.

Nb‐diffused LiTaO3 waveguides and light modulators by use of guided‐to‐radiation mode coupling

Hidetoshi Onodera, Masamitsu Nakajima, Ikuo Awai, 1984 .

MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching

Hidetoshi Onodera, Jun Shiomi, Hongjie Xu, 2021, IEEE Open Journal of Circuits and Systems.

Operational amplifier compilation with performance optimization

Hidetoshi Onodera, Keikichi Tamaru, Hiroyuki Kanbara, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

Effect ofDummyFills onHigh-Frequency Characteristics ofOn-Chip Interconnects

H. Onodera, A. Tsuchiya, 2006 .

Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPP

Kazutoshi Kobayashi, Hidetoshi Onodera, Keikichi Tamaru, 1998 .

Successive Pad Assignment for Minimizing Supply Voltage Drop

Masanori Hashimoto, Hidetoshi Onodera, Takashi Sato, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion

T. Sato, H. Onodera, M. Hashimoto, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Estimation of short-Circuit Power Dissipation for Static CMOS Gates

Hidetoshi Onodera, Keikichi Tamaru, Akio Hirata, 1996 .

A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation

Hidetoshi Onodera, Akira Tsuchiya, Islam A. K. M. Mahfuzul, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI

K. Kobayashi, H. Onodera, K. Kubota, 2013, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity

Kazutoshi Kobayashi, Hidetoshi Onodera, Jun Furuta, 2010, IEICE Trans. Electron..

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

J. Furuta, R. Yamamoto, H. Onodera, 2011, IEEE Transactions on Nuclear Science.

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element

Kazutoshi Kobayashi, Hidetoshi Onodera, Jun Furuta, 2010, 2010 Symposium on VLSI Circuits.

Crosstalk noise estimation for generic RC trees

Masanori Hashimoto, Hidetoshi Onodera, Masao Takahashi, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Improved method of loss measurement for optical waveguides by use of a rectangular glass probe.

I. Awai, H. Onodera, M. Nakajima, 1992, Applied optics.

Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement

Hidetoshi Onodera, A. K. M. Mahfuzul Islam, H. Onodera, 2017, IEEE Transactions on Semiconductor Manufacturing.

Operational-amplifier compilation with performance optimization

Hidetoshi Onodera, Keikichi Tamaru, Hiroyuki Kanbara, 1990 .

Branch-and-bound placement for building block layout

Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru, 1991, 28th ACM/IEEE Design Automation Conference.

One-pot synthesis of meso-formylporphyrins by S(N)Ar reaction of 5,15-disubstituted porphyrins with (2-pyridyldimethylsilyl)methyllithium.

H. Onodera, T. Takanami, K. Iso, 2008, Organic letters.

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing

Masaya Notomi, Akihiko Shinya, Hidetoshi Onodera, 2018, 2018 IEEE International Conference on Rebooting Computing (ICRC).

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics

Masaya Notomi, Akihiko Shinya, Hidetoshi Onodera, 2018, 2018 IEEE International Conference on Rebooting Computing (ICRC).

Characterization of WID delay variability using RO-array test structures

Hidetoshi Onodera, Haruhiko Terada, H. Onodera, 2009, 2009 IEEE 8th International Conference on ASIC.

Radiation-Induced Soft Errors

Shusuke Yoshimoto, Hiroshi Kawaguchi, Yukio Mitsuyama, 2018, VLSI Design and Test for Systems Dependability.

A yield and speed enhancement scheme under within-die variations on 90nm LUT array

Kazutoshi Kobayashi, Hidetoshi Onodera, Manabu Kotani, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Supplemental PDK for ASAP7 Using Synopsys Flow

Yih-Lang Li, Hidetoshi Onodera, Shinichi Nishizawa, 2021, IPSJ Trans. Syst. LSI Des. Methodol..

Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process

Kazutoshi Kobayashi, Hidetoshi Onodera, Jun Furuta, 2014, IEEE Transactions on Nuclear Science.

Physical-based RTN modeling of ring oscillators in 40-nm SiON and 28-nm HKMG by bimodal defect-centric behaviors

Kazutoshi Kobayashi, Hidetoshi Onodera, Takashi Matsumoto, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era

Kazutoshi Kobayashi, Hidetoshi Onodera, Masao Aramoto, 2005, IEICE Trans. Electron..

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing

H. Onodera, K. Kobayashi, M. Aramoto, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A vector-pipeline DSP for low-rate videophones

Xiang Li, Kazutoshi Kobayashi, Hidetoshi Onodera, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

Impact of RTN and NBTI on Synchronous Circuit Reliability

H. Onodera, Kazutoshi Kobayashi, Takashi Matsumoto, 2011 .

A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators

Hidetoshi Onodera, A.K.M. Mahfuzul Islam, Tatsuya Nakai, 2017, 2017 International Conference of Microelectronic Test Structures (ICMTS).

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells

Kazutoshi Kobayashi, Hidetoshi Onodera, Akira Tsuchiya, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

Hidetoshi Onodera, Hiroshi Inoue, Akira Tsuchiya, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

System design of a special-purpose computer for LSI design rule checking

Hidetoshi Onodera, Keikichi Tamaru, H. Onodera, 1987, Systems and Computers in Japan.

Equivalent waveform propagation for static timing analysis

H. Onodera, Masanori Hashimoto, Y. Yamada, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Crosstalk noise optimization by post-layout transistor sizing

H. Onodera, M. Takahashi, M. Hashimoto, 2001, ISPD '02.

Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA

Masanori Hashimoto, Hiroyuki Ochi, Hidetoshi Onodera, 2019, IEEE Transactions on Electron Devices.

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Kanbara, 2018, IEEE Embedded Systems Letters.

Proposal of a timing model for CMOS logic gates driving a CRC /spl pi/ load

H. Onodera, A. Hirata, K. Tamaru, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Modeling of Random Telegraph Noise under circuit operation — Simulation and measurement of RTN-induced delay fluctuation

Kazutoshi Kobayashi, Hidetoshi Onodera, Takashi Matsumoto, 2011, 2011 12th International Symposium on Quality Electronic Design.