Yoshiki Yamamoto

发表

Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2016, IEEE Transactions on Electron Devices.

Ultra-Low-Standby Power 6T Single-port and 8T Dual-port SRAMs on 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT Applications

Y. Shinozaki, K. Nii, Yoshiki Yamamoto, 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

H. Hada, N. Banno, T. Sakamoto, 2015 .

Electric field tweezers for characterization of liquid surface

Yoshiki Yamamoto, K. Sakai, 2006 .

Structural and electrical properties of HfLaOx films for an amorphous high-k gate insulator

Akira Toriumi, Kentaro Kyuno, Koji Kita, 2006 .

Study of La-Induced Flat Band Voltage Shift in Metal/HfLaOx/SiO2/Si Capacitors

Akira Toriumi, Kentaro Kyuno, Koji Kita, 2007 .

Doped HfO2 for Higher-k Dielectrics

A. Toriumi, Yoshiki Yamamoto, K. Kita, 2006 .

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Comprehensive analysis of low-frequency noise variability components in bulk and fully depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistor

Tomohiro Yamashita, Keiichi Maekawa, Shiro Kamohara, 2018 .

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

Tomohiro Yamashita, Hiroshi Miyatake, Yoshiki Yamamoto, 2009 .

An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

Koji Nii, Shinji Tanaka, Yohei Sawada, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Nanoscale Characterization of Microcrystalline Silicon Solar Cells by Scanning Near-Field Optical Microscopy

Yoshiki Yamamoto, T. Gotoh, T. Itoh, 2009 .