G. Maier

3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype

C. Kothandaraman, B. Himmel, J. Safran, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

T. Graves-abe, C. Kothandaraman, B. Himmel, 2014 .

A Scalable Multi-TeraOPS Core for AI Training and Inference

Swagath Venkataramani, Vijayalakshmi Srinivasan, George Gristede, 2018, IEEE Solid-State Circuits Letters.

Efficient AI System Design With Cross-Layer Approximate Computing

Swagath Venkataramani, Xiao Sun, Mingu Kang, 2020, Proceedings of the IEEE.

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference

Swagath Venkataramani, Xiao Sun, Mingu Kang, 2020, 2020 IEEE Symposium on VLSI Circuits.

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference

Joel Silberman, Swagath Venkataramani, Matthew M. Ziegler, 2018, 2018 IEEE Symposium on VLSI Circuits.

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

Toshiaki Kirihata, John Golz, Alex Hubbard, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).