S. Clerc

发表

Design methodology with body bias: From circuit to engineering

Philippe Flatresse, Sylvain Clerc, Vincent Huard, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A $225~\mu \text{m}^{2}$ Probe Single-Point Calibration Digital Temperature Sensor Using Body-Bias Adjustment in 28 nm FD-SOI CMOS

B. Nikolić, Ben Keller, P. Roche, 2018, IEEE Solid-State Circuits Letters.

A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling

Sylvain Clerc, Jean-Marc Daveau, Philippe Roche, 2010, IEEE Transactions on Nuclear Science.

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

T. Skotnicki, S. Monfray, F. Arnaud, 2008, IEEE Transactions on Electron Devices.

Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor

G. Gasiot, P. Roche, J. M. Daveau, 2014, 2014 IEEE International Reliability Physics Symposium.

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

Gilles Sicard, Marc Renaudin, Sylvain Clerc, 2011, TODE.

A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder

Gilles Sicard, Sylvain Clerc, Fady Abouzeid, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing

David Bol, Julien De Vos, Dennis Sylvester, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking

Olivier Billoint, Christian Bernard, Fabien Clermidy, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Olivier Billoint, Christian Bernard, Robin Wilson, 2015, IEEE Journal of Solid-State Circuits.

Enhanced design performance thanks to adaptative body biasing technique in FDSOI technolologies

F. Arnaud, P. Flatresse, S. Haendler, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Low-Power Event-Driven Spectrogram Extractor for Multiple Keyword Spotting: A proof of concept

S. Clerc, A. Cathelin, A. Frappé, 2023, 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS).

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology

Robin Wilson, Arnaud Virazel, Alberto Bosio, 2015, Sixteenth International Symposium on Quality Electronic Design.

Charge Collection Physical Modeling for Soft Error Rate Computational Simulation in Digital Circuits

Sylvain Clerc, Daniela Munteanu, Gilles Gasiot, 2016 .

Random-Walk Drift-Diffusion Charge-Collection Model For Reverse-Biased Junctions Embedded in Circuits

G. Gasiot, P. Roche, D. Munteanu, 2014, IEEE Transactions on Nuclear Science.

Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits

Sylvain Clerc, Philippe Roche, Jean-Luc Autran, 2014, Microelectron. Reliab..

A 45nm single power supply SRAM supporting low voltage operation down to 0.6V

S. Clerc, S. Barasinski, L. Camus, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test

Lirida A. B. Naviner, Sylvain Clerc, Fady Abouzeid, 2015, 2015 IEEE International Reliability Physics Symposium.