G. Fukano

A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

T. Sasaki, K. Kushida, A. Suzuki, 2008, 2008 IEEE Symposium on VLSI Circuits.

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.