Y. Fujimura

A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

T. Sasaki, K. Kushida, A. Suzuki, 2008, 2008 IEEE Symposium on VLSI Circuits.

A low supply voltage operation SRAM with HCI trimmed sense amplifiers

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

An 802.11ax 4 $\times$ 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

Y. Fujimura, H. Yoshida, S. Saigusa, 2018, IEEE Journal of Solid-State Circuits.

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Makoto Arai, Hiroyuki Kobayashi, Atsushi Suzuki, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers

Atsushi Kawasumi, Fumihiko Tachibana, Osamu Hirabayashi, 2010, 2010 IEEE Asian Solid-State Circuits Conference.