T. Laaksonen

A 1.2 V, 0.1 /spl mu/m gate length CMOS technology: design and process issues

M. Rodder, S. Aur, N. Yu, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

60 nm gate length dual-Vt CMOS for high performance applications

K. Kim, M. Rodder, S. Aur, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

I. Chen, D. Rogers, A. Amerasekera, 1997, International Electron Devices Meeting. IEDM Technical Digest.