H. Kokura

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

T. Sugii, K. Goto, Y. Tagawa, 2003, IEEE International Electron Devices Meeting 2003.

High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD

H. Ohta, H. Morioka, H. Kokura, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

N. Horiguchi, T. Yamamoto, S. Satoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

T. Sugii, T. Aoyama, H. Morioka, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..