S. Inagaki

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

T. Sugii, K. Goto, Y. Tagawa, 2003, IEEE International Electron Devices Meeting 2003.

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

N. Horiguchi, T. Yamamoto, S. Satoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Dependence of Sheet Resistance of CoSi2 with Gate Length of 30 nm on Thickness of Titanium Nitride Capping Layer in Co-Salicide Process

S. Inagaki, M. Kase, T. Saiki, 2007 .