S. Chang

A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

M. Liang, M. Tsai, S. Jang, 2002, Digest. International Electron Devices Meeting,.

Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

T. Schram, A. Veloso, M. Jurczak, 2008, 2008 Symposium on VLSI Technology.

Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer

A. Veloso, C. Adelmann, A. Lauwers, 2007, IEEE Electron Device Letters.

Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

A. Veloso, J. Kittl, A. Lauwers, 2008, IEEE Electron Device Letters.

Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

A. Veloso, M. Jurczak, J. Kittl, 2008, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $\hbox{Dy}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

A. Veloso, G. Pourtois, M. Jurczak, 2007, IEEE Electron Device Letters.

Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

M. Jurczak, J. Kittl, V. Paraschiv, 2007, 2007 IEEE Symposium on VLSI Technology.

Novel Analog in-Memory Compute with > 1 nA Current/Cell and 143.9 TOPS/W Enabled by Monolithic Normally-off Zn-rich CAAC-IGZO FET-on-Si CMOS Technology

Y. Kurokawa, S. Chang, T. Hirose, 2021, International Electron Devices Meeting.

Low VT metal-gate/high-k nMOSFETs — PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions

C. Adelmann, L. Ragnarsson, B. Kaczer, 2008, 2008 Symposium on VLSI Technology.

Development of Highly Manufacturable, Reliable, and Energy-Efficient Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM)

S. Z. Rahaman, Y. See, Y. Hsin, 2022, 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).