Hongyu Chen

Surfliner: a distortionless electrical signaling scheme for speed of light on-chip communications

Rui Shi, Chung-Kuan Cheng, Hongyu Chen, 2005, 2005 International Conference on Computer Design.

Optimal planning for mesh-based power distribution

A. Kahng, Chung-Kuan Cheng, Hongyu Chen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

The Y-architecture for on-chip interconnect: analysis and methodology

A. Kahng, Chung-Kuan Cheng, I. Măndoiu, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Rui Shi, Chung-Kuan Cheng, Hongyu Chen, 2007, 2007 Asia and South Pacific Design Automation Conference.

Clock distribution architectures: a comparative study

Rajeev Murgai, William W. Walker, Hongyu Chen, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

A mulitple level network approach for clock skew minimization with process variations

Chung-Kuan Cheng, Bo Yao, Hongyu Chen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Floorplan representations: Complexity and connections

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2003, TODE.

Revisiting floorplan representations

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2001, ISPD '01.

Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction

Feng Zhou, Chung-Kuan Cheng, Hongyu Chen, 2002, SLIP '02.