R. Jammy

发表

Prospect of tunneling green transistor for 0.1V CMOS

C. Hu, T. Liu, A. Javey, 2010, 2010 International Electron Devices Meeting.

Si tunnel transistors with a novel silicided source and 46mV/dec swing

C. Hu, T. Liu, P. Patel, 2010, 2010 Symposium on VLSI Technology.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

H. Nayfeh, M. Ieong, J. Kedzierski, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μA/μm

C. Hu, T. Liu, K. Jeon, 2011 .

Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI

P. Kirsch, K. Akarvardar, P. Majhi, 2010, 2010 International Electron Devices Meeting.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

M. Ieong, E. Cartier, V. Narayanan, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

High performance FDSOI CMOS technology with metal gate and high-k

Anna W. Topol, P. Kirsch, K. Guarini, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Contact Resistance Reduction to FinFET Source/Drain Using Novel Dielectric Dipole Schottky Barrier Height Modulation Method

R. Wallace, W. Loh, P. Majhi, 2011, IEEE Electron Device Letters.

300mm FinFET results utilizing conformal, damage free, ultra shallow junctions (Xj∼5nm) formed with molecular monolayer doping technique

G. Bersuker, S. Gausepohl, P. Kirsch, 2011, 2011 International Electron Devices Meeting.

InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge in ALD (La)AlOx/ZrO2 gate stack

G. Bersuker, P. Kirsch, S. Oktyabrsky, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

R. Jammy, P. Majhi, J. Lee, 2008, 2008 Symposium on VLSI Technology.

More Moore or More than Moore

P. Kirsch, W. Loh, C. Kang, 2012 .

Grain boundary-driven leakage path formation in HfO2 dielectrics

M. Porti, M. Nafría, G. Bersuker, 2011, 2010 Proceedings of the European Solid State Device Research Conference.

Grain boundary-driven leakage path formation in HfO 2 dielectrics

M. Porti, M. Nafría, G. Bersuker, 2010 .

Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs

S. Thompson, S. Suthram, R. Jammy, 2008, IEEE Electron Device Letters.

The challenges and progress of USJ formation & process integration for 32nm technology and beyond

T. Liu, Jungwoo Oh, P. Majhi, 2008, Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08).

SILICON FINFETS AS DETECTORS OF TERAHERTZ AND SUB-TERAHERTZ RADIATION

M. Shur, G. Bersuker, D. Veksler, 2011 .

Near band edge Schottky barrier height modulation using high-κ dielectric dipole tuning mechanism

R. Wallace, W. Loh, P. Majhi, 2009 .

Tunnel Oxide Dipole Engineering in TANOS Flash Memory for Fast Programming with Good Retention and Endurance

D. Gilmer, P. Kirsch, P. Majhi, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

D. Gilmer, P. Kirsch, R. Jammy, 2009, IEEE Electron Device Letters.

Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance

K. Saraswat, D. Gilmer, G. Bersuker, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration

R. Choi, C. Kang, P. Majhi, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Tunnel oxide degradation in TANOS devices and its origin

D. Gilmer, G. Bersuker, H. Hwang, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Effects of RRAM Stack Configuration on Forming Voltage and Current Overshoot

D. Gilmer, G. Bersuker, P. Kirsch, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

Hot Forming to Improve Memory Window and Uniformity of Low-Power HfOx-Based RRAMs

Y. Nishi, G. Bersuker, R. Jammy, 2012, 2012 4th IEEE International Memory Workshop.

High-Speed E-Mode InAs QW MOSFETs With $\hbox{Al}_{2} \hbox{O}_{3}$ Insulator for Future RF Applications

P. Kirsch, Daehyun Kim, J. D. del Alamo, 2013, IEEE Electron Device Letters.

High-Speed E-Mode InAs QW MOSFETs With Al 2 O 3 Insulator for Future RF Applications

P. Kirsch, Daehyun Kim, J. Alamo, 2013 .

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

P. Kirsch, W. Loh, P. Majhi, 2010, 2010 International Electron Devices Meeting.

Demonstration of High-Performance PMOSFETs Using $ \hbox{Si}$–$\hbox{Si}_{x}\hbox{Ge}_{1 - x}$ –$\hbox{Si}$ Quantum Wells With High- $\kappa$/Metal-Gate Stacks

R. Jammy, P. Majhi, R. Choi, 2008, IEEE Electron Device Letters.

InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax

D. Veksler, P. Kirsch, J. D. del Alamo, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Device design considerations for ultra-thin SOI MOSFETs

V. Narayanan, M. Steen, R. Jammy, 2003, IEEE International Electron Devices Meeting 2003.

Thermal Immune Ni Germanide for High Performance Ge MOSFETs on Ge -on- Si Substrate Utilizing $ \hbox{Ni}_{0.95}\hbox{Pd}_{0.05}$ Alloy

Won-Ho Choi, R. Jammy, Zhun Zhong, 2009 .

Thermal Immune Ni Germanide for High Performance Ge MOSFETs on Geon-Si Substrate Utilizing Ni 0 . 95 Pd 0 . 05 Alloy

P. Majhi, R. Jammy, Hi-Deok Lee, 2009 .

Improved Ge Surface Passivation With Ultrathin $ \hbox{SiO}_{X}$ Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

J.C. Lee, Hsing-Huang Tseng, Byoung Hun Lee, 2007, IEEE Electron Device Letters.

Comparative study of geometry-dependent capacitances of planar FETs and double-gate FinFETs: Optimization and process variation

Yoon-Ha Jeong, Chang Yong Kang, R. Jammy, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

SILICON FINFETS AS DETECTORS OF TERAHERTZ AND SUB-TERAHERTZ RADIATION

Michael S. Shur, Raj Jammy, G. Bersuker, 2013 .

nMOSFET Reliability Improvement attributed to the Interfacial Dipole formed by La Incorporation in HfO2

G. Bersuker, P. Kirsch, A. Kingon, 2007 .

Abrupt current increase due to space-charge-limited conduction in thin nitride–oxide stacked dielectric system

R. Jammy, Fen Chen, R. Dufresne, 2001 .

Impact of NiPt Thickness Scaling on Contact Resistance From Thin-Body FD SOI to Trigate FETs

S. Gausepohl, P. Kirsch, K. Akarvardar, 2012, IEEE Electron Device Letters.

Simultaneous optimization of short-channel effects and junction capacitance in pMOSFET using large-angle-tilt-implantation of nitrogen (LATIN)

R. Rengarajan, R. Jammy, Kilho Lee, 2002, IEEE Electron Device Letters.

Effective Modulation of Ni Silicide Schottky Barrier Height Using Chlorine Ion Implantation and Segregation

W. Loh, Jungwoo Oh, P. Majhi, 2009, IEEE Electron Device Letters.

Vth variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node

G. Bersuker, R. Jammy, P. Majhi, 2006, 2009 Symposium on VLSI Technology.

High-performance Enhancement-Mode In0.53Ga0.47As surface channels n-MOSFET with thin In0.2Ga0.8As capping and laser anneal effect

D. Veksler, P. Majhi, R. Jammy, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

Interface engineering for enhanced electron mobilities in W/HfO/sub 2/ gate stacks

A. Curioni, V. Narayanan, R. Jammy, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

P. Oldiges, K. Maitra, V. Narayanan, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Higher permittivity rare earth doped HfO2 for sub-45-nm metal-insulator-semiconductor devices

P. Kirsch, B. Lee, T. Böscke, 2007 .

Tetragonal Phase Stabilization by Doping as an Enabler of Thermally Stable HfO2 based MIM and MIS Capacitors for sub 50nm Deep Trench DRAM

P. Kirsch, S. Kudelka, J. Heitmann, 2006, 2006 International Electron Devices Meeting.

Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node

R. Jammy, P. D. Kirsch, P. Majhi, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

High temperature millisecond silicide anneal for contact resistivity < 10−8 Ωcm2

G. Bersuker, P. Kirsch, W. Loh, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Thermally Robust Ni Germanide Technology Using Cosputtering of Ni and Pt for High-Performance Nanoscale Ge MOSFETs

H. Lee, Ga-Won Lee, Min-Ho Kang, 2012, IEEE Transactions on Nanotechnology.

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors

H. Lee, Ga-Won Lee, Min-Ho Kang, 2012 .

Improvement of thermal stability of Ni-germanide with co-sputtering of nickel and palladium for high performance Ge CMOSFET

H. Lee, Min-Ho Kang, Jungwoo Oh, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

Ni Germanide Utilizing Ytterbium Interlayer for High-Performance Ge MOSFETs

H. Lee, Ga-Won Lee, Jungwoo Oh, 2009 .

High Transport Si/SiGe Heterostructures for CMOS Transistors with Orientation and Strain Enhanced Mobility

Injo Ok, Hi-Deok Lee, Jeff Huang, 2010, IEICE Trans. Electron..

High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node

R. Jammy, P. Majhi, R. Choi, 2007, 2007 IEEE International Electron Devices Meeting.

Performance and variability in multi-VT FinFETs using fin doping

P. Y. Hung, T. Ngai, R. Jammy, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Impact of Fin Doping and Gate Stack on FinFET (110) and (100) Electron and Hole Mobilities

S. Gausepohl, P. Kirsch, K. Akarvardar, 2012, IEEE Electron Device Letters.

Gate stack technology for nanoscale devices

P. Kirsch, B. Lee, R. Choi, 2006, 2006 IEEE Nanotechnology Materials and Devices Conference.

Influence of Incorporating Rare Earth Metals on the Schottky Barrier Height of Ni Silicide

H. Lee, Jungwoo Oh, P. Majhi, 2010 .

CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique

D. Canaperi, R. Jammy, M. Steen, 2004, IEEE Electron Device Letters.

Decoupling the Fermi-level pinning effect and intrinsic limitations on p-type effective work function metal electrodes

D. Kwong, G. Bersuker, B. Lee, 2008 .

ALD beryllium oxide: Novel barrier layer for high performance gate stacks on Si and high mobility substrates

G. Bersuker, P. Kirsch, E. Yu, 2011, 2011 International Electron Devices Meeting.

Carrier transport mechanism in La-incorporated high-k dielectric/metal gate stack MOSFETs

H. Lee, B. Lee, C. Kang, 2011 .

Erratum: “Comparison of Multilayer Dielectric Thin Films for Future Metal–Insulator–Metal Capacitors: Al2O3/HfO2/Al2O3 versus SiO2/HfO2/SiO2”

H. Lee, C. Kang, R. Jammy, 2011 .

S. Datta, R. Jammy, C. Hobbs, 2012 .

X-Ray Reflectometry Determination of Structural Information from Atomic Layer Deposition Nanometer-scale Hafnium Oxide Thin Films

R. Jammy, P. Hung, J. Cline, 2007 .

Detailed high-k/In0.53Ga0.47As interface understanding to enable improved In0.53Ga0.47As gate stack quality

Y. T. Chen, J. Woicik, D. Veksler, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Enhanced Performance and SRAM Stability in FinFET with Reduced Process Steps for Source/Drain Doping

J. Yang, R. Jammy, H. Tseng, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

III–V gate stack interface improvement to enable high mobility 11nm node CMOS

Y. T. Chen, J. Woicik, G. Bersuker, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Issues associated with p-type band-edge effective work function metal electrodes: Fermi-level pinning and flatband roll-off

D. Kwong, G. Bersuker, B. Lee, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Intrinsic Reliability Improvement in Biaxially Strained SiGe p-MOSFETs

G. Bersuker, S. Deora, Gerhard Klimeck, 2010, IEEE Electron Device Letters.

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

H. Lee, Ga-Won Lee, B. Lee, 2009 .

CONNECTING ELECTRICAL AND STRUCTURAL DIELECTRIC CHARACTERISTICS

L. Larcher, A. Padovani, G. Bersuker, 2011 .

Microstructural Innovation of Ni Germanide on Ge-on-Si Substrate by Using Palladium Incorporation

H. Lee, Ga-Won Lee, Chel-Jong Choi, 2009 .

Sub-10nm junction in InGaAs with sulfur mono-layer doping

P. Kirsch, W. Loh, R. Jammy, 2013, International Symposium on VLSI Technology, Systems, and Applications.

Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate/High- $k$ Dielectric SOI FinFETs

Moon J. Kim, B. Lee, R. Choi, 2008, IEEE Electron Device Letters.

Effects of metal gate-induced strain on the performance of metal-oxide-semiconductor field effect transistors with titanium nitride gate electrode and hafnium oxide dielectric

Chang Yong Kang, Byoung Hun Lee, Raj Jammy, 2007 .

Bulk and Interface effects on voltage linearity of ZrO2–SiO2 multilayered metal-insulator-metal capacitors for analog mixed-signal applications

Raj Jammy, Geun Young Yeom, Chong-Yun Park, 2009 .

Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-$k$ Dielectric/Metal Gate

Chang Yong Kang, Sang-Uk Park, Ga-Won Lee, 2011, IEEE Electron Device Letters.

CMOS Scaling with III-V Channels for Improved Performance and Low Power

P. Kirsch, W. Loh, Jungwoo Oh, 2011 .

Improved Electrical Characteristics of Ge-on-Si Field-Effect Transistors With Controlled Ge Epitaxial Layer Thickness on Si Substrates

C. Kang, Jungwoo Oh, P. Majhi, 2007, IEEE Electron Device Letters.

Analysis of trap effect on reliability using the charge pumping technology in La-incorporated high-k dielectrics

H. Lee, B. Lee, C. Kang, 2011 .

Effective Schottky Barrier Height modulation using dielectric dipoles for source/drain specific contact resistivity improvement

R. Jammy, P. D. Kirsch, K. Matthews, 2012, 2012 International Electron Devices Meeting.

Modified NiSi ∕ Si Schottky Barrier Height by Nitrogen Implantation

T. Liu, P. Majhi, R. Jammy, 2009 .

Parasitic resistance reduction technology

K. Akarvardar, W. Loh, R. Jammy, 2011, 11th International Workshop on Junction Technology (IWJT).

Dual workfunction fully silicided metal gates

J. Kedzierski, R. Carruthers, C. Cabral, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Improvement of Thermal Stability of Ni Germanide Using a Ni–Pt(1%) Alloy on Ge-on-Si Substrate for Nanoscale Ge MOSFETs

Hsing-Huang Tseng, Ga-Won Lee, R. Jammy, 2010, IEEE Transactions on Nanotechnology.

FinFET parasitic resistance reduction by segregating shallow Sb, Ge and As implants at the silicide interface

K. Matthews, S. Gausepohl, P. Kirsch, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Spectroscopic analysis of the process‐dependent microstructure of ultra‐thin high‐k gate dielectric film systems

G. Bersuker, R. Jammy, H. Tseng, 2006 .

Asymmetry, Vacancy Engineering and Mechanism for Bipolar RRAM

S. Koveshnikov, Y. Nishi, G. Bersuker, 2012, 2012 4th IEEE International Memory Workshop.

Metal oxide RRAM switching mechanism based on conductive filament microscopic properties

L. Larcher, M. Nafria, M. Porti, 2010, 2010 International Electron Devices Meeting.

Benchmarking and improving III-V Esaki diode performance with a record 2.2 MA/cm2 peak current density to enhance TFET drive current

P. Kirsch, W. Loh, R. Jammy, 2012, 2012 International Electron Devices Meeting.

Effect of Si capping layer on the interface quality and NBTI of high mobility channel Ge-on-Si pMOSFETs

H. Lee, B. Lee, C. Kang, 2009 .

Conduction Mechanism and Reliability Characteristics of a Metal–Insulator–Metal Capacitor with Single ZrO2 Layer

H. Lee, Ga-Won Lee, C. Kang, 2011 .

Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm

Chang Yong Kang, Hsing-Huang Tseng, Raj Jammy, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

Advanced techniques for achieving ultra-shallow junctions in future CMOS devices

W. Loh, P. Majhi, R. Jammy, 2010, 2010 International Workshop on Junction Technology Extended Abstracts.

Impact of Oxygen on Work Function of Ru Oxide Metal Gate

Chang Seo Park, G. Bersuker, P. Kirsch, 2010 .

Time-Dependent Dielectric Breakdown of $\hbox{La}_{2} \hbox{O}_{3}$-Doped High-$k$/Metal Gate Stacked NMOSFETs

G. Bersuker, R. Jammy, G. Bersuker, 2009, IEEE Electron Device Letters.

Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric

L. Larcher, G. Bersuker, R. Jammy, 2008, 2008 IEEE International Electron Devices Meeting.

Demonstration of $L_{g} \sim \hbox{55}\ \hbox{nm}$ pMOSFETs With $\hbox{Si/Si}_{0.25}\hbox{Ge}_{0.75}/\hbox{Si}$ Channels, High $I_{\rm on}/I_{\rm off}\ (≫ \hbox{5} \times \hbox{10}^{4})$ , and Controlled Short Channel Effects (SCEs)

Hsing-Huang Tseng, S. Datta, R. Jammy, 2008, IEEE Electron Device Letters.

Photo-enhanced negative differential resistance and photo-accelerated time-dependent dielectric breakdown in thin nitride-oxide dielectric film

R. Jammy, Fen Chen, A. Strong, 2001 .

S. Datta, B. Rajamohanan, P. Majhi, 2012, IEEE Electron Device Letters.

The Effect of a Si Capping Layer on RF Characteristics of High-$k$ /Metal Gate SiGe Channel pMOSFETs

Jack C. Lee, C. Kang, Jungwoo Oh, 2010, IEEE Electron Device Letters.

Real-time study of switching kinetics in integrated 1T/ HfOx 1R RRAM: Intrinsic tunability of set/reset voltage and trade-off with switching time

S. Koveshnikov, R. Jammy, P. D. Kirsch, 2012, 2012 International Electron Devices Meeting.

An Accurate Lifetime Analysis Methodology Incorporating Governing NBTI Mechanisms in High-k/SiO2 Gate Stacks

G. Bersuker, R. Jammy, B.H. Lee, 2006, 2006 International Electron Devices Meeting.

Understanding noise measurements in MOSFETs: the role of traps structural relaxation

M. Shur, G. Bersuker, R. Jammy, 2010, 2010 IEEE International Reliability Physics Symposium.

Interface characteristics of ZrO2 high-k gate dielectrics on epitaxial Ge capacitor layers after thermal desorption of Ge native oxide and Ge nitridation

S. Banerjee, J. Campbell, Jungwoo Oh, 2008 .

Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

D. Gilmer, G. Bersuker, P. Kirsch, 2008, Symposium on VLSI Technology.

Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate

B. H. Lee, H. Lee, C. Kang, 2008 .

Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- $k$/Metal Gate Stacks Directly on SiGe

G. Bersuker, R. Jammy, P. Majhi, 2009, IEEE Electron Device Letters.

Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Hsing-Huang Tseng, Byoung Hun Lee, R. Jammy, 2007, 2007 IEEE Symposium on VLSI Technology.

High endurance performance of 1T1R HfOx based RRAM at low (<20μA) operative current and elevated (150°C) temperature

S. Koveshnikov, Y. Nishi, G. Bersuker, 2011, 2011 IEEE International Integrated Reliability Workshop Final Report.

Advanced high-k/metal gate stack progress and challenges – a materials and process integration perspective

G. Bersuker, P. Kirsch, P. Majhi, 2010 .

Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High Temperature Stability for 32nm and Beyond

D. Gilmer, G. Bersuker, P. Kirsch, 2007, 2007 IEEE International Electron Devices Meeting.

Dielectric dipole mitigated Schottky barrier height tuning using atomic layer deposited aluminum oxide for contact resistance reduction

Moon J. Kim, R. Wallace, W. Loh, 2011 .

Mobility reduction and reliability assessment of high-k/metal gate stacks in deep sub-nanometer EOT region

G. Bersuker, P. Kirsch, R. Jammy, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Mechanism of Vfb roll-off with High Work function Metal Gate and Low Temperature Oxygen Incorporation to Achieve PMOS Band Edge Work function

R. Jammy, B.H. Lee, S.C. Song, 2007, 2007 IEEE International Electron Devices Meeting.

Achieving Band Edge Effective Work Function of Gate First Metal Gate by Oxygen Anneal Processes: Low Temperature Oxygen Anneal (LTOA) and High Pressure Oxygen Anneal (HPOA) Processes

H. Hwang, G. Bersuker, P. Kirsch, 2007 .

Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate

G. Bersuker, B. Lee, R. Choi, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Developing a systematic approach to metal gates and high-k dielectrics in future-generation CMOS

Prashant Majhi, Huang-Chun Wen, Husam N. Alshareef, 2006, MICRO 2006.

High mobility CMOS transistors on Si/SiGe heterostructure channels

Injo Ok, Raj Jammy, P. Y. Hung, 2012 .

Low power operating bipolar TMO ReRAM for sub 10 nm era

S. J. Kim, J. H. Kim, R. Jammy, 2010, 2010 International Electron Devices Meeting.

Flexible, simplified CMOS on Si(110) with metal gate / high k for HP and LSTP

P. Kirsch, S. Thompson, S. Suthram, 2007, 2007 IEEE International Electron Devices Meeting.

SiGe CMOS on (110) channel orientation with mobility boosters : Surface orientation, channel directions, and uniaxial strain

R. Jammy, P. D. Kirsch, I. Ok, 2010, 2010 Symposium on VLSI Technology.

Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application

G. Bersuker, R. Jammy, P. Majhi, 2006, 2009 Symposium on VLSI Technology.

Performance and reliability investigation of (110) and (100) sidewall oriented MugFETs

G. Bersuker, P. Kirsch, K. Akarvardar, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

Husam N. Alshareef, Muhammad Mustafa Hussain, Gennadi Bersuker, 2008 .

Reliability Characteristics of La-doped High-k/Metal Gate nMOSFETs

Byoung Hun Lee, Raj Jammy, Rino Choi, 2009 .

Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel

P. Kirsch, K. Tateiwa, R. Jammy, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-$k$/Metal Gates CMOS FinFETs for Multi- $V_{\rm Th}$ Engineering

Hsing-Huang Tseng, R. Jammy, M.M. Hussain, 2010, IEEE Transactions on Electron Devices.

Additive Process Induced Strain (APIS) Technology for L g = 30nm Band-Edge High-k/Metal Gate nMOSFET

P. Kirsch, S. Suthram, R. Jammy, 2008 .

Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack

P. Kirsch, B. Lee, R. Jammy, 2007 .

A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si (1hannel for Both N and PMOSFETs

G. Bersuker, R. Jammy, B.H. Lee, 2006, 2006 International Electron Devices Meeting.

A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

D. Gilmer, G. Bersuker, P. Kirsch, 2006, 2009 Symposium on VLSI Technology.

Reliability assessment of low |Vt| metal high-κ gate stacks for high performance applications

G. Bersuker, P. Kirsch, C. Kang, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Reliability of La-Doped Hf-Based Dielectrics nMOSFETs

Chang Yong Kang, Hsing-Huang Tseng, Byoung Hun Lee, 2009, IEEE Transactions on Device and Materials Reliability.

A comprehensive and comparative study of interface and bulk characteristics of nMOSETs with la-incorporated high-k dielectrics

G. Bersuker, H. Lee, B. Lee, 2008, 2008 IEEE International Electron Devices Meeting.

Band Edge n-MOSFETs with High-k/Metal Gate Stacks Scaled to EOT=0.9nm with Excellent Carrier Mobility and High Temperature Stability

G. Bersuker, P. Kirsch, A. Kingon, 2006, 2006 International Electron Devices Meeting.

Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric

R. Jammy, B.H. Lee, P. Majhi, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Work function engineering using lanthanum oxide interfacial layers

Husam N. Alshareef, Byoung Hun Lee, Raj Jammy, 2006 .

on-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained $ \hbox{Si}_{0.5}\hbox{Ge}_{0.5}$ Quantum-Well pMOSFET Along $ \langle \hbox{110} \rangle$ and $\langle \hbox{100} \rangle$ Channel Directions

Leonard Franklin Register, Raj Jammy, Aneesh Nainani, 2011, IEEE Transactions on Electron Devices.

Composition dependence of the work function of Ta1−xAlxNy metal gates

B. Lee, R. Wallace, P. Majhi, 2006 .

Effect of substrate hot carrier stress on high-k gate stack

G. Bersuker, R. Jammy, H. Tseng, 2008, 2008 IEEE International Integrated Reliability Workshop Final Report.

Role of oxygen vacancies in V/sub FB//V/sub t/ stability of pFET metals on HfO/sub 2/

E. Cartier, F.R. McFeely, V. Narayanan, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Study of piezoresistance under unixial stress for technologically relevant III-V semiconductors using wafer bending experiments

K. Saraswat, A. Nainani, P. Majhi, 2010 .

The progress and challenges of threshold voltage control of high-k/metal-gated devices for advanced technologies (Invited Paper)

Hsing-Huang Tseng, Raj Jammy, Gennadi Bersuker, 2009 .