M. Masahara

发表

Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform

K. Endo, T. Mori, Y. Morita, 2014, 2014 IEEE International Electron Devices Meeting.

Variability Analysis of Scaled Crystal Channel and Poly-Si Channel FinFETs

K. Endo, T. Matsukawa, S. O'uchi, 2012, IEEE Transactions on Electron Devices.

Heated ion implantation for high-performance and highly reliable silicon-on-insulator complementary metal–oxide–silicon fin field-effect transistors

K. Endo, Y. Morita, W. Mizubayashi, 2015 .

Heated ion implantation technology for highly reliable metal-gate/high-k CMOS SOI FinFETs

K. Endo, Y. Morita, W. Mizubayashi, 2013, 2013 IEEE International Electron Devices Meeting.

Fluctuation Analysis of Parasitic Resistance in FinFETs With Scaled Fin Thickness

K. Endo, T. Matsukawa, S. O'uchi, 2009, IEEE Electron Device Letters.

Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs

K. Endo, Y. Morita, W. Mizubayashi, 2014 .

A Correlative Analysis Between Characteristics of FinFETs and SRAM Performance

K. Endo, T. Matsukawa, S. O'Uchi, 2012, IEEE Transactions on Electron Devices.

Comprehensive analysis of variability sources of FinFET characteristics

K. Endo, T. Matsukawa, S. O'uchi, 2006, 2009 Symposium on VLSI Technology.

Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching

E. Suzuki, K. Ishii, T. Matsukawa, 2004, IEEE Transactions on Electron Devices.

Synthetic electric field tunnel FETs: Drain current multiplication demonstrated by wrapped gate electrode around ultrathin epitaxial channel

K. Endo, T. Mori, Y. Morita, 2013, 2013 Symposium on VLSI Technology.

The Guideline of Si/SiGe Hetero-Junction Design in Parallel Plate Style TFETs (PP-TFETs) for Si CMOS Platform Implementation

S. Kawanaka, Y. Morita, S. Migita, 2014 .

Novel Device Architecture Proposal of Source Junctionless Tunneling Field-Effect Transistor (SJL-TFET)

S. Kawanaka, T. Mori, Y. Morita, 2014 .

Independent double-gate FinFETs with asymmetric gate stacks

K. Devriendt, M. Jurczak, E. Suzuki, 2007 .

Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs With Asymmetric Gate-Oxide Thicknesses

E. Suzuki, K. Ishii, K. Endo, 2007, IEEE Electron Device Letters.

Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm

K. Endo, T. Matsukawa, S. O'uchi, 2012, IEEE Transactions on Electron Devices.

Bias temperature instability in tunnel field-effect transistors

K. Endo, Y. Morita, K. Fukuda, 2017 .

ON current enhancement of nanowire Schottky barrier tunnel field effect transistors

T. Matsukawa, M. Masahara, Takanobu Watanabe, 2016 .

Impact of thermal history of Si nanowire fabrication process on Ni silicidation rate

Jing Sun, Takashi Matsukawa, Meishoku Masahara, 2014 .

Demonstration, analysis, and device design considerations for independent DG MOSFETs

E. Suzuki, K. Ishii, K. Endo, 2005, IEEE Transactions on Electron Devices.

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

T. Chikyow, K. Endo, T. Nabatame, 2015 .

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

K. Endo, Y. Morita, W. Mizubayashi, 2014 .

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

T. Chikyow, K. Endo, T. Nabatame, 2014 .

1=f noise characteristics of fin-type field-effect transistors in saturation region

K. Endo, H. Ishikuro, T. Matsukawa, 2013 .

Analysis of threshold voltage shifts in double gate tunnel FinFETs: Effects of improved electrostatics by gate dielectrics and back gate effects

K. Endo, T. Matsukawa, S. O'uchi, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Hiromi Yamauchi, Kunihiro Sakamoto, T. Hayashida, 2012 .

Independent-Double-Gate FINFET SRAM Cell for Drastic Leakage Current Reduction

E. Suzuki, K. Ishii, K. Endo, 2010 .

Experimental Investigation of Optimum Gate Workfunction for CMOS Four-Terminal Multigate MOSFETs (MUGFETs)

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Transactions on Electron Devices.

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Electron Device Letters.

Advanced FinFET CMOS Technology: TiN-Gate, Fin-Height Control and Asymmetric Gate Insulator Thickness 4T-FinFETs

K. Endo, T. Matsukawa, S. O'uchi, 2006, 2006 International Electron Devices Meeting.

Demonstration of Asymmetric Gate Oxide Thickness 4-Terminal FinFETs

M. Masahara, L. Witters, C. Vrancken, 2006, 2006 IEEE international SOI Conferencee Proceedings.

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

H. Yamauchi, M. Masahara, H. Takashima, 2004, IEEE Electron Device Letters.

Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs

K. Endo, T. Matsukawa, H. Yamauchi, 2007, IEEE Electron Device Letters.

Metal-Gate FinFET Variation Analysis by Measurement and Compact Model

K. Endo, T. Matsukawa, H. Yamauchi, 2009, IEEE Electron Device Letters.

Independent double-gate FinFET SRAM technology

Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo, 2011 .

Characterization of metal-gate FinFET variability based on measurements and compact model analyses

E. Suzuki, K. Ishii, K. Endo, 2008, 2008 IEEE International Electron Devices Meeting.

On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs

K. Endo, T. Matsukawa, S. O'Uchi, 2010, 2010 Symposium on VLSI Technology.

Advanced FinFET process technology for 20 nm node and beyond

K. Endo, Y. Morita, W. Mizubayashi, 2011, The 4th IEEE International NanoElectronics Conference.

Comprehensive analysis of Ion variation in metal gate FinFETs for 20nm and beyond

Hiromi Yamauchi, Kunihiro Sakamoto, Takashi Matsukawa, 2011, 2011 International Electron Devices Meeting.

Enhancing SRAM cell performance by using independent double-gate FinFET

E. Suzuki, K. Ishii, K. Endo, 2008, 2008 IEEE International Electron Devices Meeting.

Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

K. Endo, Y. Morita, W. Mizubayashi, 2012, IEEE Transactions on Electron Devices.

Nanoscale TiN wet etching and its application for FinFET fabrication

K. Endo, T. Matsukawa, S. O'uchi, 2009, 2009 International Semiconductor Device Research Symposium.

Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Byung-Gook Park, Seongjae Cho, Meishoku Masahara, 2009, 2009 International Semiconductor Device Research Symposium.

Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm)

M. Masahara, H. Ota, S. Migita, 2012, 2012 International Electron Devices Meeting.

Investigation of N-Channel Triple-Gate Metal-Oxide-Semiconductor Field-Effect Transistors on (100) Silicon On Insulator Substrate

E. Suzuki, K. Ishii, K. Endo, 2006 .

Investigation of Low-Energy Tilted Ion Implantation for Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Extension Doping

K. Endo, T. Matsukawa, S. O'Uchi, 2010 .

Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction

K. Endo, T. Matsukawa, H. Yamauchi, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition

K. Endo, T. Matsukawa, S. O'Uchi, 2012 .

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

E. Suzuki, K. Ishii, K. Endo, 2006, IEEE Transactions on Nanotechnology.

Atomic layer deposition of 25-nm-thin sidewall spacer for enhancement of FinFET performance

K. Endo, T. Matsukawa, M. Masahara, 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Nanoscale Wet Etching of Physical-Vapor-Deposited Titanium Nitride and Its Application to Sub-30-nm-Gate-Length Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication

K. Endo, T. Matsukawa, S. O'Uchi, 2010 .

A Comparative Study of Nitrogen Gas Flow Ratio Dependence on the Electrical Characteristics of Sputtered Titanium Nitride Gate Bulk Planar Metal–Oxide–Semiconductor Field-Effect Transistors and Fin-Type Metal–Oxide–Semiconductor Field-Effect Transistors

E. Suzuki, K. Ishii, K. Endo, 2009 .

Nitrogen Gas Flow Ratio and Rapid Thermal Annealing Temperature Dependences of Sputtered Titanium Nitride Gate Work Function and Their Effect on Device Characteristics

E. Suzuki, K. Ishii, K. Endo, 2008 .

Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography

Kenichi Ishii, H. Takashima, Toshiyuki Tsutsumi, 2003 .

Dopant profiling in vertical ultrathin channels of double-gate metal–oxide–semiconductor field-effect transistors by using scanning nonlinear dielectric microscopy

E. Suzuki, K. Endo, T. Matsukawa, 2004 .

Diagnostics of doping integrity in n+/p/n+ transistor-channel structure by scanning nonlinear dielectric microscopy

T. Matsukawa, M. Masahara, H. Tanoue, 2004 .

Impact of extension implantation conditions of fin field-effect transistors on gate-induced drain leakage

Y. Morita, S. Migita, T. Matsukawa, 2016 .

A Novel Process for Fabrication of Gated Silicon Field Emitter Array Taking Advantage of Ion Bombardment Retarded Etching

M. Masahara, I. Ohdomari, I. Matsuya, 2005 .

Simulation study of short-channel effects of tunnel field-effect transistors

K. Endo, Y. Morita, K. Fukuda, 2018 .

Work function controllability of metal gates made by interdiffusing metal stacks with low and high work functions

E. Suzuki, K. Ishii, K. Endo, 2005 .

Work function uniformity of Al–Ni alloys obtained by scanning Maxwell-stress microscopy as an effective tool for evaluating metal transistor gates

E. Suzuki, T. Matsukawa, M. Masahara, 2005 .

Programmable Conductivity of Silicon Nanowires with Side Gates by Surface Charging

T. Matsukawa, M. Masahara, H. Tanoue, 2003 .

Impact of atomic-scale structural design on ultra-short channel (3 nm) MOSFETs

Y. Morita, S. Migita, M. Masahara, 2013, 2013 IEEE 5th International Nanoelectronics Conference (INEC).

Doping integrity diagnostics of planar transistor channel structures by scanning nonlinear dielectric microscopy

E. Suzuki, T. Matsukawa, M. Masahara, 2006 .

Accurate profiling of PN junction carrier concentration by scanning nonlinear dielectric microscopy (SNDM)

M. Masahara, T. Matsukawa, H. Tanoue, 2004, The Fourth International Workshop on Junction Technology, 2004. IWJT '04..

Investigation of Thermal Stability of TiN Film Formed by Atomic Layer Deposition Using Tetrakis(dimethylamino)titanium Precursor for Metal-Gate Metal–Oxide–Semiconductor Field-Effect Transistor

K. Endo, T. Matsukawa, S. O'Uchi, 2010 .

Study of tunneling transport in Si-based tunnel field-effect transistors with ON current enhancement utilizing isoelectronic trap

Y. Morita, K. Fukuda, W. Mizubayashi, 2015 .

Band-to-band tunneling current enhancement utilizing isoelectronic trap and its application to TFETs

Y. Morita, K. Fukuda, S. Migita, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Epitaxial growth of Ge thin film on Si (001) by DC magnetron sputtering

Y. Morita, S. Migita, T. Matsukawa, 2017 .

Cross-Sectional Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors

E. Suzuki, K. Ishii, M. Masahara, 2004 .

Study of gate leakage current paths in p-channel tunnel field-effect transistor by current separation measurement and device simulation

Y. Morita, K. Fukuda, W. Mizubayashi, 2015 .

Spatial variation of the work function in nano-crystalline TiN films measured by dual-mode scanning tunneling microscopy

Takashi Matsukawa, Meishoku Masahara, Koichi Fukuda, 2014 .

Impact of granular work function variation in a gate electrode on low-frequency noise for fin field-effect transistors

K. Endo, Y. Morita, K. Fukuda, 2015 .

Influence of work function variation of metal gates on fluctuation of sub-threshold drain current for fin field-effect transistors with undoped channels

K. Endo, Y. Morita, W. Mizubayashi, 2014 .

Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function

K. Endo, Y. Morita, W. Mizubayashi, 2013 .

Suppressed variability of current-onset voltage of FinFETs by improvement of work function uniformity of metal gates

K. Endo, Y. Morita, W. Mizubayashi, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Suppressing Vt and Gm variability of FinFETs using amorphous metal gates for 14 nm and beyond

K. Endo, T. Matsukawa, S. O'uchi, 2012, 2012 International Electron Devices Meeting.

Ultra-compact 8 × 8 strictly-non-blocking Si-wire PILOSS switch.

Ken Tanizawa, Shu Namiki, Keijiro Suzuki, 2014, Optics express.

Variability Analysis of TiN Metal-Gate FinFETs

Hiromi Yamauchi, Kunihiro Sakamoto, Takashi Matsukawa, 2010, IEEE Electron Device Letters.

Fabrication of a Vertical-Channel Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Using a Neutral Beam Etching

E. Suzuki, K. Ishii, K. Endo, 2006 .

Doping diagnosis by evaluation of the surface Fermi level using scanning Maxwell-stress microscopy

T. Matsukawa, M. Masahara, H. Tanoue, 2003 .

Silicon nanowire with programmable conductivity analyzed by scanning Maxwell-stress microscopy

T. Matsukawa, M. Masahara, H. Tanoue, 2003 .

Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology

K. Endo, T. Matsukawa, H. Yamauchi, 2006, IEEE Transactions on Electron Devices.

Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application

K. Endo, T. Matsukawa, S. O'uchi, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

A Ta/Mo Interdiffusion Dual Metal Gate Technology for Drivability Enhancement of FinFETs

E. Suzuki, K. Ishii, K. Endo, 2008, IEEE Electron Device Letters.

Low activation energy, high-quality oxidation of Si and Ge using neutral beam

K. Endo, M. Masahara, S. Samukawa, 2011 .

Low Temperature, Beam-Orientation-Dependent, Lattice-Plane-Independent, and Damage-Free Oxidation for Three-Dimensional Structure by Neutral Beam Oxidation

Takashi Matsukawa, Meishoku Masahara, Seiji Samukawa, 2009 .

Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process

Hiromi Yamauchi, Kunihiro Sakamoto, Kenichi Ishii, 2003 .

Fabrication of ultrathin Si Channel Wall For Vertical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG MOSFET) by Using Ion-Bombardment-Retarded Etching (IBRE)

Kenichi Ishii, Takashi Matsukawa, Meishoku Masahara, 2003 .

Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI

Takashi Matsukawa, Meishoku Masahara, Shinji Migita, 2014, IEEE Transactions on Nanotechnology.

Suppression of tunneling rate fluctuations in tunnel field-effect transistors by enhancing tunneling probability

Y. Morita, K. Fukuda, W. Mizubayashi, 2017 .

Silicon nanowire memory using surface charging and its operation analysis by scanning Maxwell-stress microcopy (SMM)

T. Matsukawa, M. Masahara, M. Nagao, 2001, 2001 International Semiconductor Device Research Symposium. Symposium Proceedings (Cat. No.01EX497).

Independent-Double-Gate FinFET SRAM for Leakage Current Reduction

K. Endo, T. Matsukawa, H. Yamauchi, 2009, IEEE Electron Device Letters.

Introduction of SiGe/Si heterojunction into novel multilayer tunnel FinFET

K. Endo, Y. Morita, K. Fukuda, 2015 .

Accurate prediction of PBTI lifetime for N-type fin-channel tunnel FETs

K. Endo, T. Matsukawa, S. O'uchi, 2014, 2014 IEEE International Electron Devices Meeting.

Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes

Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Importance of interface engineering for synthesis of SrHfO3 perovskite thin films on Si substrates through crystallization of amorphous films and control of flat-band voltages of metal–oxide–semiconductor capacitors

Y. Morita, S. Migita, M. Masahara, 2014 .

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations

Takashi Matsukawa, Meishoku Masahara, K. Fukuda, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel

H. Yamauchi, M. Masahara, H. Takashima, 2003, IEEE International Electron Devices Meeting 2003.

Fabrication and Power-Management Demonstration of Four-Terminal FinFETs

Meishoku Masahara, Shin-ichi O'uchi, Kazuhiko Endo, 2007 .

A novel approach to Au nanoparticle-based identification of DNA nanoarrays.

T. Matsukawa, M. Masahara, I. Ohdomari, 2007, Frontiers in bioscience : a journal and virtual library.

Fabrication and characterization of vertical-type double-gate metal-oxide-semiconductor field-effect transistor with ultrathin Si channel and self-aligned source and drain

E. Suzuki, K. Ishii, K. Endo, 2006 .

High-Performance Three-Terminal Fin Field-Effect Transistors Fabricated by a Combination of Damage-Free Neutral-Beam Etching and Neutral-Beam Oxidation

K. Endo, S. Yamasaki, T. Matsukawa, 2010 .

Charge trapping type FinFET flash memory with Al2O3 blocking layer

T. Chikyow, K. Endo, T. Nabatame, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdiffusion Dual Metal-Gate Technology for Low-Operating-Power Application

E. Suzuki, K. Ishii, K. Endo, 2008, IEEE Transactions on Electron Devices.

Dual-Metal-Gate Transistors with Symmetrical Threshold Voltages Using Work-Function-Tuned Ta/Mo Bilayer Metal Gates

E. Suzuki, K. Ishii, K. Endo, 2008 .

Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO2 gate stacks

Meishoku Masahara, Shinji Migita, Yukinori Morita, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Atomic Layer Deposition of SiO2 for the Performance Enhancement of Fin Field Effect Transistors

K. Endo, T. Matsukawa, S. O'Uchi, 2013 .

Electron mobility in multi-FinFET with a (111) channel surface fabricated by orientation-dependent wet etching

Hiromi Yamauchi, Kenichi Ishii, M. Masahara, 2005 .

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

K. Endo, Y. Morita, K. Fukuda, 2017 .

Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

In Man Kang, James S. Harris, Sang Wan Kim, 2010 .

Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect

Takashi Matsukawa, Meishoku Masahara, Shinji Migita, 2014, IEEE Electron Device Letters.

Effect of hot implantation on ON-current enhancement utilizing isoelectronic trap in Si-based tunnel field-effect transistors

Y. Morita, K. Fukuda, W. Mizubayashi, 2015 .

Structural and electrical characterization of epitaxial Ge thin films on Si(001) formed by sputtering

Y. Morita, S. Migita, T. Matsukawa, 2017 .

Scaling Silicon Photonic Switch Fabrics for Data Center Interconnection Networks References and Links Programmable Wavelength Locking and Routing in a Silicon-photonic Interconnection Network

Qi Li, Keren Bergman, Payman Samadi, 2022 .

Vertical ultrathin‐channel multi‐gate MOSFETs (MuGFETs): technological challenges and future developments

Meishoku Masahara, Yongxun Liu, Kazuhiko Endo, 2009 .

Low temperature microwave annealed FinFETs with less Vth variability

P. Sung, Y. Lee, K. Endo, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching

M. Masahara, K. Ishii, T. Tsutsumi, 2003, IEEE Electron Device Letters.