Y. Yamamoto

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias

T. Hiramoto, T. Iwamatsu, H. Oda, 2013, 2013 Symposium on VLSI Circuits.

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE International Electron Devices Meeting.

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

T. Iwamatsu, T. Hiramoto, H. Oda, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications

T. Hiramoto, S. Kamohara, H. Oda, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Design consideration of 0.4V-operation SOTB MOSFET for super low power application

T. Iwamatsu, H. Oda, Y. Inoue, 2011, 2011 International Meeting for Future of Electron Devices.

Geomagnetic paleosecular variation for the past 5 Ma in the Society Islands, French Polynesia

Y. Yamamoto, E. Kikawa, T. Yamazaki, 2002 .

Ultra-low power and ultra-low voltage devices and circuits for IoT applications

T. Saraya, T. Hiramoto, S. Kamohara, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).