H. Shinohara

发表

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias

T. Hiramoto, T. Iwamatsu, H. Oda, 2013, 2013 Symposium on VLSI Circuits.

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

Takayasu Sakurai, Hiroshi Fuketa, Makoto Takamiya, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates

Takayasu Sakurai, Hiroshi Fuketa, Makoto Takamiya, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture

K. Mashiko, H. Makino, H. Shinohara, 1996 .

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE International Electron Devices Meeting.

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

S. Kayano, H. Shinohara, Y. Kohno, 1987 .

A refreshable analog VLSI neural network chip with 400 neurons and 40 k synapses

H. Shinohara, A. Maeda, Y. Arima, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 35 ns 16K NMOS static RAM

H. Shinohara, M. Yoshimoto, T. Nakano, 1982, IEEE Journal of Solid-State Circuits.

A 24-b 50-ns digital image signal processor

Masahiko Yoshimoto, Hiroshi Segawa, Shinichi Nakagawa, 1990 .

Accurate Nanopower Supply-Insensitive CMOS Unit Vth Extractor and αVth Extractor with Continuous Variety

Jing Wang, Yasuaki Inoue, Qiang Li, 2017, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

A 3.5ppm/°C 0.85V Bandgap Reference Circuit without Resistors

Jing Wang, Yasuaki Inoue, Qiang Li, 2016, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

Steroid profile analysis and UGT2B17 genotyping of the same urine sample to determine testosterone abuse

H. Shinohara, M. Ueki, K. Aoki, 2014, Forensic Toxicology.

A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)

Hiroaki Suzuki, Tadashi Sumi, Hiroshi Makino, 1996 .

A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement

H. Shinohara, Ruilin Zhang, Xingyu Wang, 2022, IEEE Journal of Solid-State Circuits.

36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In

Hirofumi Shinohara, Kunyang Liu, Hongliang Pu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

M. Yabuuchi, K. Nii, Y. Tsukamoto, 2009, 2009 Symposium on VLSI Circuits.

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

K. Ishibashi, M. Yabuuchi, H. Makino, 2007, IEEE Journal of Solid-State Circuits.

Design consideration of a static memory cell

Masahiko Yoshimoto, Hirofumi Shinohara, Takao Nakano, 1983 .

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement

H. Shinohara, Yuxin Wang, Xuanzhen Wang, 2022, 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement

Hirofumi Shinohara, Kunyang Liu, Hongliang Pu, 2021, IEEE Journal of Solid-State Circuits.

A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement

Hirofumi Shinohara, Kunyang Liu, Fan Yang, 2021, 2021 Symposium on VLSI Circuits.

A 373-F2 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and ${V}_{\text{SS}}$ Bias-Based Dark-Bit Detection

Hirofumi Shinohara, Xuan Yang, Kunyang Liu, 2020, IEEE Journal of Solid-State Circuits.

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

H. Shinohara, M. Yoshimoto, K. Anami, 1983, IEEE Journal of Solid-State Circuits.

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

M. Yabuuchi, H. Makino, K. Nii, 2009, IEEE Journal of Solid-State Circuits.

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

T. Iwasaki, M. Yabuuchi, K. Usui, 2008, 2008 IEEE Symposium on VLSI Circuits.

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

M. Yabuuchi, T. Terano, H. Makino, 2008, IEEE Journal of Solid-State Circuits.

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

H. Suzuki, Koichiro Mashiko, H. Shinohara, 1996, IEEE J. Solid State Circuits.

A CMOS 0.85-V 15.8-nW Current and Voltage Reference without Resistors

Hirofumi Shinohara, Jing Wang, H. Shinohara, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in

Kunyang Liu, Hirofumi Shinohara, Hongliang Pu, 2020, 2020 IEEE Custom Integrated Circuits Conference (CICC).

A 1.2GFLOPS neural network chip exhibiting fast convergence

Hirofumi Shinohara, Hiroyuki Amishiro, Y. Arima, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Takayasu Sakurai, Hirofumi Shinohara, Atsushi Kawasumi, 2013, IEEE Journal of Solid-State Circuits.