Y. Yamaguchi

发表

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias

T. Hiramoto, T. Iwamatsu, H. Oda, 2013, 2013 Symposium on VLSI Circuits.

A 1 V 46 ns 16 Mb SOI-DRAM with body control technique

K. Kyuma, T. Eimori, S. Maegawa, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

Analytical Device Model of SOI MOSFETs Including Self-Heating Effect

K. Taniguchi, Y. Yamaguchi, N. Yasuda, 1991 .

Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate length

Hans-Oliver Joachim, Y. Inoue, Y. Yamaguchi, 1993 .

New carrier lifetime measurement method for fully depleted SOI MOSFET's

Kenji Taniguchi, Nishimura Tadashi, N. Yasuda, 1992 .

On the scaling limit of the Si-IGBTs with very narrow mesa structure

A. Sakai, Y. Yamaguchi, M. Inuishi, 2016, 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD).

First demonstration of FinFET split-gate MONOS for high-speed and highly-reliable embedded flash in 16/14nm-node and beyond

D. Hisamoto, K. Sonoda, T. Yamashita, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

Y. Inoue, T. Iwamatsu, H. Oda, 1994 .

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE International Electron Devices Meeting.

Subthreshold Slope in Ultra Thin-Film SOI MOSFET's and Its Two-Dimensional Analytical Modeling down to 0.1μm Gate Length

K. Tsukamoto, Y. Yamaguchi, Y. Yamaguchi, 1992 .

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2001 .

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

T. Iwamatsu, T. Hiramoto, H. Oda, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications

T. Hiramoto, S. Kamohara, H. Oda, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Revisited study of fluorine implantation impact on negative bias temperature instability for input/output device of automotive micro controller unit

Y. Yamaguchi, Tatsuo Shimizu, S. Tsuda, 2018 .

Investigation of leakage current in pinned photodiode CMOS imager pixel with negative transfer-gate bias operation

Y. Yamaguchi, T. Kunikiyo, M. Tanizawa, 2015, 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

TCAD Analysis of Source-Side Injection Program of FinFET Split-Gate MONOS

K. Sonoda, T. Yamashita, Y. Yamaguchi, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Analysis of the Effect of Field Enhancement at Fin Corners on Program Characteristics of FinFET Split-Gate MONOS

K. Sonoda, T. Yamashita, Y. Yamaguchi, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A method for the prediction of hot-carrier lifetime in floating SOI NMOSFETs

S. Maeda, Y. Inoue, H. Miyoshi, 1997 .

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

T. Eimori, Y. Inoue, T. Iwamatsu, 1994, IEEE International Solid-State Circuits Conference.

Study on the improved short-circuit behavior of narrow mesa Si-IGBTs with emitter connected trenches

A. Sakai, Y. Yamaguchi, K. Eikyu, 2018, 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD).

Suppression of floating body effects in SOI–MOSFET studied using nuclear microprobes

Y. Yamaguchi, M. Takai, Nishimura Tadashi, 2001 .

Two-Dimensional Analytical Modeling of the Source/Drain Engineering Influence on Short-Channel Effects in SOI MOSFET's

Y. Inoue, Y. Yamaguchi, H. Joachim, 1995 .

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)

Hideto Hidaka, Katsuhiro Suma, Kazuyasu Fujishima, 1996 .

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

Y. Akasaka, Y. Yamaguchi, K. Fujibayashi, 1992 .

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

K. Ishibashi, M. Yabuuchi, H. Makino, 2007, IEEE Journal of Solid-State Circuits.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

Y. Yamaguchi, A. Hiraiwa, S. Shimamoto, 2010 .

A high speed 0.6- mu m 16 K CMOS gate array on a thin SIMOX film

Katsuhiro Tsukamoto, Masahiro Shimizu, Y. Yamaguchi, 1993 .

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Comprehensive analysis of low-frequency noise variability components in bulk and fully depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistor

Tomohiro Yamashita, Keiichi Maekawa, Shiro Kamohara, 2018 .

Embedded flash technology for automotive applications

Hideto Hidaka, Tadaaki Yamauchi, Takashi Kono, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Ultra-low power and ultra-low voltage devices and circuits for IoT applications

T. Saraya, T. Hiramoto, S. Kamohara, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

Hideto Hidaka, T. Iwamatsu, Takahiro Tsuruda, 1993, Proceedings of IEEE International Electron Devices Meeting.

Effects of metal impuritites on the etch rate selectivity of (110)/(111) in (110) Si anisotropic etching

Teruo Usami, Yoshiaki Hirata, Koji Tanimoto, 1999, Photonics West - Micro and Nano Fabricated Electromechanical and Optical Components.

Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Electron trap level of hydrogen incorporated nitrogen vacancies in silicon nitride

K. Sonoda, Y. Yamaguchi, M. Tanizawa, 2015 .

An analysis of the effect of hydrogen incorporation on electron traps in silicon nitride

K. Sonoda, K. Ishikawa, Y. Yamaguchi, 2014, 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Iwamatsu, Narumi Sakashita, Masahide Inuishi, 1998 .

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

T. Iwamatsu, Yasuo Inoue, N. Tsubouchi, 1995 .

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM

T. Eimori, Y. Yamaguchi, M. Yamada, 1999 .

A study of SRAM NBTI by OTF measurement

K. Shiga, E. Murakami, K. Yanagisawa, 2008, 2008 IEEE International Reliability Physics Symposium.