C. Hsieh

发表

Focal-plane-arrays and CMOS readout techniques of infrared imaging systems

Chih-Cheng Hsieh, Chung-Yu Wu, Tai-Ping Sun, 1997, IEEE Trans. Circuits Syst. Video Technol..

A new CMOS readout circuit design for the IR FPA with adaptive gain control and current-mode background suppression

Chung-Yu Wu, C. Hsieh, F. Jih, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

New design techniques for a complementary metal-oxide semiconductor current readout integrated circuit for infrared detector arrays

Chung-Yu Wu, C. Hsieh, 1995 .

A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip

Meng-Fan Chang, Chih-Cheng Hsieh, Chia-Hsiang Yang, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A new CMOS image sensor readout structure for 3D integrated imagers

Chih-Cheng Hsieh, Chung-Chi Jim Li, Jin-Yi Lin, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2020, IEEE Journal of Solid-State Circuits.

A new cryogenic CMOS readout structure for infrared focal plane array

Chung-Yu Wu, C. Hsieh, T. Sun, 1997, IEEE J. Solid State Circuits.

High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA

Chung-Yu Wu, C. Hsieh, F. Jih, 1998, IEEE J. Solid State Circuits.

Design, optimization, and performance analysis of new photodiode structures for CMOS active-pixel-sensor (APS) imager applications

Chung-Yu Wu, C. Hsieh, Yu-Chuan Shih, 2004 .

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices

Meng-Fan Chang, Tzu-Hsiang Hsu, Wei-Chen Wei, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

P 35 Low Dark Current UV-VIS Planar-electrode Perovskite CMOS Image Sensor

C. Hsieh, Pei-Wen Yen, Cheng-Hung Hou, 2017 .

A hybrid CMOS-imager with perovskites as photoactive layer

C. Hsieh, Pei-Wen Yen, Shengqing Yu, 2016, 2016 IEEE SENSORS.

A 32-Stage 15-b Digital Time-Delay Integration Linear CMOS Image Sensor With Data Prediction Switching Technique

C. Hsieh, Chin-Fong Chiu, Chin Yin, 2017, IEEE Transactions on Electron Devices.

A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise

Chih-Cheng Hsieh, Meng-Ting Chung, C. Hsieh, 2012, 2012 IEEE International Solid-State Circuits Conference.

A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetry

Chih-Cheng Hsieh, Chin-Fong Chiu, Kuan-Lin Liu, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks

Meng-Fan Chang, C. Hsieh, K. Tang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

Meng-Fan Chang, Xiaoyu Sun, Shimeng Yu, 2020, IEEE Journal of Solid-State Circuits.

CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2019, Nature Electronics.

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Yen-Cheng Chiu, Wei-Chen Wei, Ren-Shuo Liu, 2020, Nature Electronics.

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

Meng-Fan Chang, Qiang Li, Tzu-Hsiang Hsu, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Shih-Chieh Chang, Meng-Fan Chang, Shanshi Huang, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Meng-Fan Chang, Shimeng Yu, Yen-Cheng Chiu, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

C. Lo, W. Lo, Meng-Fan Chang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

Meng-Fan Chang, Tzu-Hsiang Hsu, Ren-Shuo Liu, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices

Y. Chih, C. Lo, Meng-Fan Chang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, IEEE Journal of Solid-State Circuits.

24.1 A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Y. Chih, C. Lo, Meng-Fan Chang, 2020, Nature Electronics.

A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification

C. Lo, Meng-Fan Chang, C. Hsieh, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction

Meng-Fan Chang, Ren-Shuo Liu, Kea-Tiong Tang, 2021, IEEE Journal of Solid-State Circuits.

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization

Chih-Cheng Hsieh, Chen-Che Kao, Sung-En Hsieh, 2018, IEEE Journal of Solid-State Circuits.

A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia

Meng-Fan Chang, Chih-Cheng Hsieh, Yi-Wen Liu, 2014, IEEE Transactions on Biomedical Circuits and Systems.

A Miniature Electronic Nose for Breath Analysis

C. Hsieh, Ting-I Chou, Shih-Wen Chiu, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices

Y. Chih, C. Lo, Meng-Fan Chang, 2021, Nature Electronics.

AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device

Tzu-Hsiang Hsu, Yen-Cheng Chiu, Wei-Chen Wei, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices

Meng-Fan Chang, Tzu-Hsiang Hsu, Yen-Cheng Chiu, 2019, 2019 Symposium on VLSI Technology.

Exploration of Second-Order Effects in High-Performance Continuous-Time $\Sigma\Delta$ Modulators Using Discrete-Time Models

Chih-Cheng Hsieh, Wei-Lin Chen, C. Hsieh, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

New switch-current integration readout structure for infrared focal plane arrays

Chung-Yu Wu, Far-Wen Jih, Tai Ping Sun, 1994, Optics & Photonics.

A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System

Meng-Fan Chang, Chih-Cheng Hsieh, Jyuo-Min Shyu, 2011, IEEE Transactions on Biomedical Circuits and Systems.

A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS

Chih-Cheng Hsieh, Chang-Yuan Liou, C. Hsieh, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

Jin-Yi Lin, Chih-Cheng Hsieh, C. Hsieh, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Linear-Logarithmic CMOS Image Sensor With Pixel-FPN Reduction and Tunable Response Curve

Chih-Cheng Hsieh, Wei-Fan Chou, Shang-Fu Yeh, 2014, IEEE Sensors Journal.

A Current-Mode Differential Sensing CMOS Imager for Optical Linear Encoder

Tzu-Hsiang Hsu, Chih-Cheng Hsieh, Chien-Wen Chen, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

C. Lo, W. Lo, Meng-Fan Chang, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

An integrated CMOS optical sensing chip for multiple bio-signal detections

Chih-Cheng Hsieh, Albert Yen-Chih Chiou, Sung-En Hsieh, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

An 8-bit column-shared SAR ADC for CMOS image sensor applications

Chih-Cheng Hsieh, Jin-Yi Lin, Shih-Chin Lo, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

Chih-Cheng Hsieh, Jin-Yi Lin, Pei-Chen Lee, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

A CMOS imaging platform using single photon avalanche diode array in standard technology

Tzu-Hsiang Hsu, Chih-Cheng Hsieh, C. Hsieh, 2017, 2017 IEEE SENSORS.

Design, optimization, and performance analysis of new photodiode structures for CMOS active-pixel-sensor (APS) imager applications

Chung-Yu Wu, C. Hsieh, Jeng-Feng Lan, 2004, IEEE Sensors Journal.

A 0.5 V, 14.28-kframes/s, 96.7-dB Smart Image Sensor With Array-Level Image Signal Processing for IoT Applications

Chih-Cheng Hsieh, Chin-Fong Chiu, Chin Yin, 2016, IEEE Transactions on Electron Devices.

A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique

Tzu-Hsiang Hsu, Chih-Cheng Hsieh, Ting Liao, 2018, IEEE Journal of Solid-State Circuits.

A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel

Tzu-Hsiang Hsu, Chung-Chuan Lo, Ren-Shuo Liu, 2021, IEEE Journal of Solid-State Circuits.

A 137 dB Dynamic Range and 0.32 V Self-Powered CMOS Imager With Energy Harvesting Pixels

Chih-Cheng Hsieh, Albert Yen-Chih Chiou, C. Hsieh, 2016, IEEE Journal of Solid-State Circuits.

An ULV PWM CMOS Imager With Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting

Chih-Cheng Hsieh, Albert Yen-Chih Chiou, C. Hsieh, 2019, IEEE Journal of Solid-State Circuits.

A novel single slope ADC design for wide dynamic range CMOS image sensors

Chih-Cheng Hsieh, Shang-Fu Yeh, Chun-Kai Liu, 2011, 2011 IEEE SENSORS Proceedings.

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations

Y. Chih, C. Lo, Chieh-Pu Lo, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices

Y. Chih, C. Lo, Meng-Fan Chang, 2023, IEEE Journal of Solid-State Circuits.

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

Chih-Cheng Hsieh, Sung-En Hsieh, C. Hsieh, 2018, IEEE Journal of Solid-State Circuits.

A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS

Chih-Cheng Hsieh, Jin-Yi Lin, C. Hsieh, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Xin Si, Shyh-Shyuan Sheu, Ting-Wei Chang, 2022, IEEE Journal of Solid-State Circuits.

A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS

Chih-Cheng Hsieh, Sung-En Hsieh, C. Hsieh, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

Meng-Fan Chang, Wei-Hao Chen, Yen-Cheng Chiu, 2020, IEEE Journal of Solid-State Circuits.

A 12b 10MS/s 18.9fJ/conversion-step sub-radix-2 SAR ADC

Chih-Cheng Hsieh, Kwuang-Han Chang, C. Hsieh, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction

Meng-Fan Chang, Wei-Chen Wei, Ren-Shuo Liu, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices

Y. Chih, C. Lo, Chieh-Pu Lo, 2023, Nature Electronics.

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array

Meng-Fan Chang, Tzu-Hsiang Hsu, Wei-Chen Wei, 2018, 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Linear CMOS image sensor with time-delay integration and interlaced super-resolution pixel

Chih-Cheng Hsieh, Hann-Huei Tsai, Jui-Hsin Chang, 2012, 2012 IEEE Sensors.

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips

C. Lo, C. Hsieh, K. Tang, 2024, IEEE Journal of Solid-State Circuits.

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

C. Lo, C. Hsieh, K. Tang, 2024, IEEE Journal of Solid-State Circuits.

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

C. Lo, W. Lo, Meng-Fan Chang, 2023, IEEE Journal of Solid-State Circuits.

A 0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with input-range-adaptive switching

Chih-Cheng Hsieh, Chen-Che Kao, Pei-Chen Lee, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).