Yu-hsin Chen

发表

Designing processor-memory interfaces with monolithically integrated silicon-photonics

V. Stojanović, Chen Sun, Yu-hsin Chen, 2013, 2013 Conference on Lasers and Electro-Optics Pacific Rim (CLEOPR).

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

Vivienne Sze, Joel S. Emer, Yu-Hsin Chen, 2017, Proceedings of the IEEE.

Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices

Vivienne Sze, Tien-Ju Yang, Yu-Hsin Chen, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Understanding the Limitations of Existing Energy-Efficient Design Approaches for Deep Neural Networks

J. Emer, Yu-hsin Chen, Tien-Ju Yang, 2018 .

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

Chen Sun, Karan Mehta, Rajeev J. Ram, 2015, IEEE J. Solid State Circuits.

Integration of silicon photonics in bulk CMOS

Rajeev J Ram, M. Popović, V. Stojanović, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process

Aravind Srinivasan, Chen Sun, Vladimir Stojanovic, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

Vivienne Sze, Joel S. Emer, Tushar Krishna, 2017, IEEE Journal of Solid-State Circuits.

Hardware for Machine Learning : Challenges and Opportunities ( Invited Paper )

V. Sze, J. Emer, Amr Suleiman, 2017 .

Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks

Joel Emer, Vivienne Sze, Yu-Hsin Chen, 2018, ArXiv.

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

V. Sze, J. Emer, Yu-hsin Chen, 2016, IEEE Journal of Solid-State Circuits.

TOPS/W (alone) Considered Harmful

V. Sze, J. Emer, Yu-hsin Chen, 2020 .

Hardware for machine learning: Challenges and opportunities

V. Sze, J. Emer, Amr Suleiman, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

V. Sze, J. Emer, Yu-hsin Chen, 2016, IEEE Journal of Solid-State Circuits.

A method to estimate the energy consumption of deep neural networks

Joel Emer, Vivienne Sze, Tien-Ju Yang, 2017, 2017 51st Asilomar Conference on Signals, Systems, and Computers.

Efficient Processing of Deep Neural Networks

Joel Emer, Vivienne Sze, Tien-Ju Yang, 2020, Synthesis Lectures on Computer Architecture.

Single-chip microprocessor that communicates directly using light

Rajeev J. Ram, Fabio Pavanello, Mark T. Wade, 2015, Nature.

Designing Energy-Efficient Convolutional Neural Networks Using Energy-Aware Pruning

Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, 2016, 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR).

How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful

Vivienne Sze, Joel S. Emer, Tien-Ju Yang, 2020, IEEE Solid-State Circuits Magazine.

Timeloop: A Systematic Approach to DNN Accelerator Evaluation

Brucek Khailany, Stephen W. Keckler, Joel S. Emer, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks pdf

Vivienne Sze, Joel S. Emer, Yu-Hsin Chen, 2018, ArXiv.

Architecture design for highly flexible and energy-efficient deep neural network accelerators

Yu-Hsin Chen, Yu-hsin Chen, 2018 .

Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators

Vivienne Sze, Joel S. Emer, Yu-Hsin Chen, 2017, IEEE Micro.

Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper)

Vivienne Sze, Joel S. Emer, Yu-Hsin Chen, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Hardware for machine learning: Challenges and opportunities

Vivienne Sze, Zhengdong Zhang, Yu-Hsin Chen, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

Vivienne Sze, Joel S. Emer, Yu-Hsin Chen, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

Heterogeneous Dataflow Accelerators for Multi-DNN Workloads

Hyoukjun Kwon, Tushar Krishna, Vikas Chandra, 2020, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Eyeriss: an Energy-efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks Accessed Terms of Use

Joel Emer, Vivienne Sze, Tushar Krishna, 2022 .

Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform

Douglas Coolbaugh, Vladimir Stojanovic, Sen Lin, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 24-GHz Receiver Frontend With an LO Signal Generator in 0.18-$\mu$m CMOS

Liang-Hung Lu, Hsieh-Hung Hsieh, Yu-Hsin Chen, 2008, IEEE Transactions on Microwave Theory and Techniques.

Collisions in dispersion-managed soliton propagation.

H. Haus, Yu-hsin Chen, 1999 .

Locally-connected and convolutional neural networks for small footprint speaker recognition

Tara N. Sainath, Mirkó Visontai, Ignacio Lopez-Moreno, 2015, INTERSPEECH.

Hardware for machine learning: Challenges and opportunities

V. Sze, Amr Suleiman, Zhengdong Zhang, 2016, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Efficient Processing of Deep Neural Networks

V. Sze, J. Emer, Yu-hsin Chen, 2020, Synthesis Lectures on Computer Architecture.

RETROSPECTIVE: Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

J. Emer, Yu-hsin Chen, EnCharge, 2023 .

A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications

Vivienne Sze, Yu-Hsin Chen, V. Sze, 2014, IEEE Transactions on Circuits and Systems for Video Technology.

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

V. Sze, J. Emer, Yu-hsin Chen, 2016, IEEE Journal of Solid-State Circuits.

Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

Vladimir Stojanović, Miloš A. Popović, Rajeev J. Ram, 2015, Photonics West - Optoelectronic Materials and Devices.

Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

V. Sze, J. Emer, Yu-hsin Chen, 2016, International Symposium on Computer Architecture.

Heterogeneous Dataflow Accelerators for Multi-DNN Workloads

Liangzhen Lai, V. Chandra, Michael Pellauer, 2020, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Low Power Depth Estimation of Rigid Objects for Time-of-Flight Imaging

V. Sze, J. Emer, Yu-hsin Chen, 2021 .

Artificial Intelligence Machine Learning Brain-Inspired Spiking Neural Networks Deep Learning

V. Sze, Yu-hsin Chen, 2017 .

14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

V. Sze, J. Emer, Yu-hsin Chen, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).