W. Choi

发表

Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration

T. Liu, W. Choi, Hei Kam, 2007, 2007 IEEE International Electron Devices Meeting.

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Byung-Gook Park, T. Liu, W. Choi, 2007, IEEE Electron Device Letters.

Ambipolarity characterization of tunneling field-effect transistors

W. Choi, Jung-Shik Jang, 2010, 2010 Silicon Nanoelectronics Workshop.

Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling

T. Liu, W. Choi, T. Osabe, 2008, IEEE Transactions on Electron Devices.

Nanoelectromechanical Memory Cell (T Cell) for Low-Cost Embedded Nonvolatile Memory Applications

Woo Young Choi, W. Choi, Kwangseok Lee, 2011, IEEE Transactions on Electron Devices.

A unified model for unipolar resistive random access memory

Keun-Ho Lee, Young-Kwan Park, W. Choi, 2012 .

Design and scaling of nano-electro-mechanical non-volatile memory (NEMory) cells

W. Choi, 2010 .

Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices.

J. Shim, C. Shin, Jung‐Dong Park, 2015, Nano letters.

Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical Hybrid Reconfigurable Circuits

W. Choi, Yong Jun Kim, 2015, IEEE Electron Device Letters.

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS–NEM Hybrid Circuits

W. Choi, H. Jo, 2018, Micromachines.

Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

W. Choi, Woojun Lee, 2010, IEEE Transactions on Electron Devices.

Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field

W. Choi, Sangwan Kim, 2017 .

Vertical-Structured Electron-Hole Bilayer Tunnel Field-Effect Transistor for Extremely Low-Power Operation With High Scalability

Byung-Gook Park, W. Choi, Sangwan Kim, 2018, IEEE Transactions on Electron Devices.

Hump Effects of Germanium/Silicon Heterojunction Tunnel Field-Effect Transistors

Woo Young Choi, Sang Wan Kim, W. Choi, 2016, IEEE Transactions on Electron Devices.

Demonstration of L-Shaped Tunnel Field-Effect Transistors

Woo Young Choi, Byung-Gook Park, J. Kim, 2016, IEEE Transactions on Electron Devices.

Design guideline of tunnel field-effect transistors (TFETs) considering negative differential transconductance (NDT)

W. Choi, J. Lee, 2020 .

Effects of abnormal cell-to-cell interference on p-type floating gate and control gate NAND flash memory

Woo Young Choi, Sung-Kye Park, Byungin Lee, 2014 .

Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

W. Choi, 2017 .

Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage

W. Choi, 2020, Micromachines.

A sub-0.5 V operating RF low noise amplifier using tunneling-FET

W. Choi, J. Jeon, H. Jhon, 2017 .

Monolithic three-dimensional tunnel FET–nanoelectromechanical hybrid reconfigurable logic circuits

W. Choi, Seung Kyu Kim, S. Kim, 2017 .

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs)

W. Choi, Hyun Kook Lee, 2016, Nano Convergence.

Effect of Device Parameters on the Breakdown Voltage of Impact-Ionization Metal–Oxide–Semiconductor Devices

W. Choi, 2009 .

Dual random circuit breaker network model with equivalent thermal circuit network

Woo Young Choi, Kwanyong Kim, S. J. Yoon, 2014 .

Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions

W. Choi, H. Jhon, Gyuhan Yoon, 2017 .

Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)

Woo Young Choi, Gibong Lee, W. Choi, 2012, IEICE Trans. Electron..

Linearity of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

W. Choi, Hyun Kook Lee, 2013 .

Influence of Inversion Layer on Tunneling Field-Effect Transistors

Woojun Lee, W. Choi, Woojun Lee, 2011, IEEE Electron Device Letters.

Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall

Jong-Ho Lee, W. Choi, I. Cho, 2013 .

Active directional beaming by mechanical actuation of double-sided plasmonic surface gratings.

Byoungho Lee, W. Choi, Hwi Kim, 2013, Optics letters.

Pull-In Voltage Modeling of Graphene Formed Nickel Nano Electro Mechanical Systems (NEMS)

Jong-Ho Lee, W. Choi, I. Cho, 2015 .

Charge trap length dependence and transconductance characteristics of a 2T SONOS cell

W. Choi, Ji-Song Lim, Sung-Kun Park, 2014, 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS).

Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor

W. Choi, I. Cho, E. Cho, 2014 .

Physically Consistent Method for Calculating Trap-Assisted-Tunneling Current Applied to Line Tunneling Field-Effect Transistor

W. Choi, Sangwan Kim, Y. Yu, 2020, IEEE Transactions on Electron Devices.

Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation

Woo Young Choi, Hyug Su Kwon, Seung Kyu Kim, 2017, IEEE Electron Device Letters.

Scaling Trends of Monolithic 3-D Complementary Metal–Oxide–Semiconductor Nanoelectromechanical Reconfigurable Logic Circuits

Woo Young Choi, Gwangryeol Baek, Ji Wang Ko, 2020, IEEE Transactions on Electron Devices.

Multi-Layer Nanoelectromechanical (NEM) Memory Switches for Multi-Path Routing

W. Choi, J. Yoon, H. Kwon, 2022, IEEE Electron Device Letters.

Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

Woo Young Choi, Yong Jun Kim, W. Choi, 2015, IEEE Transactions on Electron Devices.

In-Memory Nearest Neighbor Search With Nanoelectromechanical Ternary Content-Addressable Memory

W. Choi, J. Yoon, Jae Seong Lee, 2022, IEEE Electron Device Letters.

Island-Style Monolithic Three-Dimensional CMOS-Nanoelectromechanical Logic Circuits

Woo Young Choi, Hyug Su Kwon, Ji Wang Ko, 2020, IEEE Electron Device Letters.

Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State

Woo Young Choi, Gwangryeol Baek, Jisoo Yoon, 2020, IEEE Access.

Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage

W. Choi, Gyuhan Yoon, Kyung Min Koo, 2021, Micromachines.

Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory

Il Hwan Cho, Woo Young Choi, Dongsun Seo, 2013, IEICE Trans. Electron..

70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)

Woo Young Choi, Byung-Gook Park, Young June Park, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Nanoelectromechanical-Switch-Based Binary Content-Addressable Memory (NEMBCAM)

Woo Young Choi, Jae Seong Lee, W. Choi, 2021, IEEE Access.

Radio Frequency Performance of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

W. Choi, I. Kang, Jung-Shik Jang, 2011 .

Influence of Fringe Field on Nano-Electromechanical (NEM) Memory Cells

W. Choi, Boram Han, Ji Yong Song, 2014, IEEE Transactions on Nanotechnology.

LTPS TFTs with an Amorphous Silicon Buffer Layer and Source/Drain Extension

W. Choi, Yong Jo Kim, H. Kim, 2020, Electronics.

Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs)

Woo Young Choi, W. Choi, Min Jin Lee, 2011 .

Random Dopant Fluctuation Effects of Tunneling Field-Effect Transistors ( TFETs ) ) 장 정 식

W. Choi, Jung-Shik Jang, Hyun Kook Lee, 2012 .

Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

W. Choi, I. Kang, Jae Sung Lee, 2012 .

Design Guidelines for Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs)

Woo Young Choi, Jang Woo Lee, W. Choi, 2020, IEEE Access.

Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

W. Choi, Min Jin Lee, 2012, IEEE Electron Device Letters.

An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs

W. Choi, M. Shin, I. Huh, 2017, IEEE Transactions on Electron Devices.

Triple-gate Tunnel FETs Encapsulated with an Epitaxial Layer for High Current Drivability

W. Choi, J. Lee, 2017 .

Design Guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors

Min-Chul Sun, Woo Young Choi, Byung-Gook Park, 2012 .

Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs)

Woo Young Choi, W. Choi, Kyoung Min Choi, 2013, IEEE Electron Device Letters.

Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nanoelectromechanical (NEM) Hybrid Circuits

W. Choi, 2018, 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM).

Monolithic 3D (M3D) reconfigurable logic applications using extremely-low-power electron devices

Woo Young Choi, W. Choi, 2017, 2017 China Semiconductor Technology International Conference (CSTIC).

Dynamic Slingshot Operation for Low-Operation- Voltage Nanoelectromechanical (NEM) Memory Switches

Min Hee Kang, Woo Young Choi, W. Choi, 2020, IEEE Access.

Switching Voltage Analysis of Nanoelectromechanical Memory Switches for Monolithic 3-D CMOS-NEM Hybrid Reconfigurable Logic Circuits

W. Choi, H. Jo, H. Kwon, 2018, IEEE Transactions on Electron Devices.

Double bi-material cantilever structures for complex surface plasmon modulation.

Byoungho Lee, Woo Young Choi, Jaebum Cho, 2015, Optics express.

A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement

W. Choi, Woojun Lee, 2011, IEEE Transactions on Nanotechnology.

A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors

Woo Young Choi, Younghoon Cho, Gyuhan Yoon, 2019, Micromachines.

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

W. Choi, Sang–Hee Lee, H. Kwon, 2022, Electronics.

Influence of line-edge roughness on multiple-gate tunnel field-effect transistors

W. Choi, 2017 .

Germanium electron–hole bilayer tunnel field-effect transistors with a symmetrically arranged double gate

Seok-Hee Lee, W. Choi, Min Gyu Albert Park, 2015 .

Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

W. Choi, Minji Kang, 2020, Applied Sciences.