Hung-Jen Liao

发表

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications

Jonathan Chang, Michael Clinton, Hank Cheng, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Sreedhar Natarajan, Shien-Yang Wu, Hung-Jen Liao, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

Hidehiro Fujiwara, Po-Yi Huang, Jonathan Chang, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 45nm dual-port SRAM with write and read capability enhancement at low voltage

Hiroyuki Yamauchi, Y. H. Chen, Hung-Jen Liao, 2007, 2007 IEEE International SOC Conference.

Improving the speed and power of compilable SRAM using dual-mode self-timed technique

Meng-Fan Chang, Shu-Meng Yang, Hung-Jen Liao, 2007, 2007 IEEE International Workshop on Memory Technology, Design and Testing.

An efficient tabu search for cell planning problem in mobile communication

Jain-Shing Liu, Chun-Hung Richard Lin, Hung-Jen Liao, 2016, Wirel. Commun. Mob. Comput..

A large σVTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Yuan-Hua Chu, 2010, 2010 Symposium on VLSI Circuits.

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

Meng-Fan Chang, Hiroyuki Yamauchi, Che-Wei Wu, 2011, 2011 IEEE International Solid-State Circuits Conference.

Network Traffic Analysis with Cloud Platform

Shih-Lin Wu, Hung-Jen Liao, Ying Chih Lin, 2012 .

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications

Jonathan Chang, Hung-Jen Liao, Ching-Wei Wu, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

The importance of DFX, a foundry perspective

Saman Adham, Jonathan Chang, John Hung, 2014, 2014 International Test Conference.

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Meng-Fan Chang, Hiroyuki Yamauchi, Che-Wei Wu, 2013, IEEE Journal of Solid-State Circuits.

A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Yuan-Hua Chu, 2011, IEEE Journal of Solid-State Circuits.

A 40nm fully functional SRAM with BL swing and WL pulse measurement scheme for eliminating a need for additional sensing tolerance margins

Meng-Fan Chang, Ping Wang, Hiroyuki Yamauchi, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Intrusion detection system: A comprehensive review

Chun-Hung Richard Lin, Hung-Jen Liao, Ying-Chih Lin, 2013, J. Netw. Comput. Appl..

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

Min Cao, Sreedhar Natarajan, Hank Cheng, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

Mahmut E. Sinangil, Hung-Jen Liao, Yen-Ting Lin, 2019, IEEE Journal of Solid-State Circuits.

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS

Jonathan Chang, Ming-Hung Chang, Hung-Jen Liao, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

Jonathan Chang, Qing Dong, Hung-Jen Liao, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications

Hidehiro Fujiwara, Jonathan Chang, Hung-Jen Liao, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

Meng-Fan Chang, Ping Wang, Hiroyuki Yamauchi, 2012, IEEE Journal of Solid-State Circuits.

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

Hidehiro Fujiwara, Tsung-Yung Jonathan Chang, Hung-Jen Liao, 2021, IEEE Journal of Solid-State Circuits.

A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology

Yen-Ting Lin, Jonathan Chang, Mahmut E. Sinangil, 2018, 2018 IEEE Symposium on VLSI Circuits.

Detection of SRAM cell stability by lowering array supply voltage

Ding-Ming Kwai, Yung-Fa Chou, Hung-Jen Liao, 2000, Proceedings of the Ninth Asian Test Symposium.

A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

Jonathan Chang, Shien-Yang Wu, Hung-Jen Liao, 2014, IEEE Journal of Solid-State Circuits.

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Meng-Fan Chang, Hiroyuki Yamauchi, Yung-Chi Chen, 2009, IEEE Journal of Solid-State Circuits.

A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

Hidehiro Fujiwara, Jonathan Chang, Hung-Jen Liao, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Hidehiro Fujiwara, Tan-Li Chou, Yu-Der Chih, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).