H. Fukutome

发表

Comprehensive extensibility of 20nm low power/high performance technology platform featuring scalable high-k/metal gate planar transistors with reduced design corner

H. Fukutome, K. Cheon, J. P. Kim, 2012, 2012 International Electron Devices Meeting.

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

T. Sugii, T. Aoyama, H. Morioka, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Carrier profile designing to suppress systematic Vth variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects

S. Satoh, H. Minakata, Y. Momiyama, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Direct measurement of carrier profiles in operating sub-30-nm N-MOSFETs

T. Itakura, T. Aoyama, Y. Momiyama, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Two-Dimensional Carrier Profiling by Scanning Tunneling Microscopy and Its Application to Advanced Device Development

Hidenobu Fukutome, H. Fukutome, 2010 .

Two-dimensional characterization of carrier concentration in metal-oxide-semiconductor field-effect transistors with the use of scanning tunneling microscopy

H. Fukutome, H. Arimoto, S. Hasegawa, 2004 .

Gate insulating layer impact on the extension profile of the sub-50 nm p-MOSFET

H. Ohta, M. Hori, H. Fukutome, 2002, Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT..

Anomalous diffusion in the extension region of nanoscale MOSFETs

T. Aoyama, H. Fukutome, H. Arimoto, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Scanning tunneling microscopy study of annealing effects on Si nanoscaled pn junctions formed by ion implantation

T. Aoyama, H. Fukutome, H. Arimoto, 1999, Digest of Papers. Microprocesses and Nanotechnology '99. 1999 International Microprocesses and Nanotechnology Conference.

Visualization of the depleted layer in nanoscaled pn junctions on Si(001) surfaces with the use of scanning tunneling microscopy

T. Aoyama, H. Fukutome, H. Arimoto, 1999 .

Direct imaging of nano pn junctions and their bulk electronic properties with the use of scanning tunneling microscopy

T. Aoyama, H. Fukutome, H. Arimoto, 1998 .

Scanning tunneling microscopy study of the hydrogen-terminated n- and p-type Si(001) surfaces

H. Fukutome, K. Maehashi, S. Hasegawa, 1998 .

Characterization of a 0.1 /spl mu/m MOSFET using cross-sectional scanning tunneling microscopy

H. Fukutome, H. Arimoto, S. Hasegawa, 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs

Y. Momiyama, T. Aoyama, Y. Tagawa, 2006, IEEE Transactions on Electron Devices.

Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs

Y. Momiyama, T. Aoyama, Y. Tagawa, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Direct measurement of effects of shallow-trench isolation on carrier profiles in sub-50 nm N-MOSFETs

T. Aoyama, Y. Nara, Y. Tagawa, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Visualization of 0.1-μm-metal-oxide-semiconductor field-effect transistors by cross-sectional scanning tunneling microscopy

H. Fukutome, H. Arimoto, S. Hasegawa, 2002 .

Fluorine implantation impact in extension region on the electrical performance of sub-50nm P-MOSFETs

H. Nakao, Y. Momiyama, T. Aoyama, 2003, IEEE International Electron Devices Meeting 2003.

Advanced technologies for enhancing drive current of high-density transistors

Y. Momiyama, H. Fukutome, 2009, 2009 International Workshop on Junction Technology.

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

S. Satoh, T. Sugii, H. Ohta, 2007, 2007 IEEE International Electron Devices Meeting.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

Y. S. Nam, J. H. Lee, K. H. Lee, 2016, 2016 IEEE Symposium on VLSI Technology.