S. Biesemans

发表

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

O. Richard, H. Bender, N. Collaert, 2008, 2008 Symposium on VLSI Technology.

Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs

O. Richard, H. Bender, N. Collaert, 2008, 2008 IEEE International SOI Conference.

Calibrated PSCAR stochastic simulation

Geert Vandenberghe, Hans-Jürgen Stock, Peter De Bisschop, 2019, Advanced Lithography.

Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

T. Schram, A. Veloso, M. Jurczak, 2008, 2008 Symposium on VLSI Technology.

1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

A. Hikavyy, H. Dekkers, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Layout impact on the performance of a locally strained PMOSFET

A. De Keersgieter, R. Degraeve, M. Jurczak, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Review of FINFET technology

N. Collaert, A. Veloso, S. Biesemans, 2009, 2009 IEEE International SOI Conference.

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

R. Rooyackers, Liesbeth Witters, C. Ortolland, 2009, 2009 Proceedings of ESSCIRC.

FinFETs and Their Futures

N. Horiguchi, N. Collaert, A. Veloso, 2011 .

Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability

N. Horiguchi, B. Parvais, T. Hoffmann, 2011, 2011 IEEE ICMTS International Conference on Microelectronic Test Structures.

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

A. Hikavyy, N. Collaert, M. Jurczak, 2007, 2007 IEEE Symposium on VLSI Technology.

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

A. Hikavyy, K. Devriendt, S. Demuynck, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Migrating from planar to FinFET for further CMOS scaling: SOI or Bulk?

Rita Rooyackers, Liesbeth Witters, C. Ortolland, 2009, ESSDERC 2009.

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

Rita Rooyackers, Nadine Collaert, Malgorzata Jurczak, 2008 .

On the effective mobility for electrons in MOS inversion channels

S. Biesemans, K. De Meyer, K. De Meyer, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

Sub 0.1 /spl mu/m nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivity

K. Maex, S. Kubicek, K. De Meyer, 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

On the Integral Representations of Electrical Characteristics in Si Devices

K. Meyer, S. Biesemans, 1995 .

Accurate determination of channel length, series resistance and junction doping profile for MOSFET optimisation in deep submicron technologies

S. Kubicek, K. De Meyer, S. Biesemans, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Fundamental relation between local and effective transverse field dependent mobility for electrons in inversion channels

K. De Meyer, S. Biesemans, 1996, 1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095).

Defining a ‘charge vector’ and its use in the treatment of the short channel effect in deep submicron MOSFETs

K. Meyer, S. Biesemans, 1997 .

Test structure to investigate the series resistance components of source/drain structure

S. Kubicek, K. De Meyer, S. Biesemans, 1997, IEEE Electron Device Letters.

Direct measurement of l/sub eff/ and channel profile in MOSFETs using 2-D carrier profiling techniques

P. Jansen, K. De Meyer, S. Biesemans, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Analytical Calculation of Subthreshold Slope Increase in Short-Channel MOSFET's by Taking Drift Component into Account

K. Meyer, S. Biesemans, 1995 .

Electric Field Reduced Charging Energies and Two-Electron Bound Excited States of Single Donors in Silicon

N. Collaert, S. Biesemans, G. Klimeck, 2011, 1107.2701.

3D stacked IC demonstration using a through Silicon Via First approach

A. Jourdain, E. Beyne, B. Parvais, 2008, 2008 IEEE International Electron Devices Meeting.

Gatestacks for scalable high-performance FinFETs

A. Hikavyy, N. Collaert, M. Jurczak, 2007, 2007 IEEE International Electron Devices Meeting.

Performance improvement of tall triple gate devices with strained SiN layers

E. Sleeckx, A. De Keersgieter, N. Collaert, 2005, IEEE Electron Device Letters.

Temperature dependent electrical characteristics of through-si-via (TSV) interconnections

A. Jourdain, E. Beyne, A. Mercha, 2010, 2010 IEEE International Interconnect Technology Conference.

Independent double-gate FinFETs with asymmetric gate stacks

K. Devriendt, M. Jurczak, E. Suzuki, 2007 .

Hot carrier reliability for 0.13 /spl mu/m CMOS technology with dual gate oxide thickness

T. Schiml, C. Wann, S. Biesemans, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Layout density analysis of FinFETs

N. Collaert, S. Biesemans, K.G. Anil, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

T. Schram, O. Richard, H. Bender, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Demonstration of Metal-Gated Low $V_{t}$ n-MOSFETs Using a Poly-$\hbox{Si/TaN/Dy}_{2}\hbox{O}_{3}/\hbox{SiON}$ Gate Stack With a Scaled EOT Value

T. Schram, C. Adelmann, V. Chang, 2007, IEEE Electron Device Letters.

Metal Inserted Poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration

S. Kubicek, P. Jaenen, M. Demand, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

S. De Gendt, N. Collaert, W. Boullart, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs

M. Rosmeulen, M. Jurczak, A. Mercha, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL

B. Ghyselen, R. Rooyackers, N. Collaert, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Tall triple-gate device with TiN/HfO2 gate stack

Paul Zimmerman, Tom Schram, Stefan De Gendt, 2005 .

Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs

N. Collaert, Gerhard Klimeck, S. Biesemans, 2010, IEEE Electron Device Letters.

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

R. Rooyackers, N. Collaert, S. Biesemans, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

B. Parvais, S. Biesemans, T. Schram, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Experimental Investigation of Optimum Gate Workfunction for CMOS Four-Terminal Multigate MOSFETs (MUGFETs)

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Transactions on Electron Devices.

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Electron Device Letters.

Demonstration of Asymmetric Gate Oxide Thickness 4-Terminal FinFETs

M. Masahara, L. Witters, C. Vrancken, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Gate-induced quantum-confinement transition of a single dopant atom in a silicon FinFET

Insoo Woo, Gerhard Klimeck, Nadine Collaert, 2008 .

Widely Tunable Work Function TaN/Ru Stacking Layer on HfLaO Gate Dielectric

G. Lo, D. Kwong, H. Yu, 2008, IEEE Electron Device Letters.

Work Function Tunability of Refractory Metal Nitrides by Lanthanum or Aluminum Doping for Advanced CMOS Devices

G. Lo, D. Kwong, Y. Yeo, 2007, IEEE Transactions on Electron Devices.

Wide $V_{\rm fb}$ and $V_{\rm th}$ Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics

G. Lo, D. Kwong, Y. Yeo, 2007, IEEE Electron Device Letters.

Leff extraction for sub-100 nm MOSFET devices

Serge Biesemans, Qiuyi Ye, Q. Ye, 2004 .

Simulation of Semiconductor Processes and Devices 1998: SISPAD 98

Serge Biesemans, Kristin De Meyer, Processes, 2012 .

Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON

A. Veloso, K. Opsomer, M. Jurczak, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

PSCAR optimization to reduce EUV resist roughness with sensitization using Resist Formulation Optimizer (RFO)

Geert Vandenberghe, Hans-Jürgen Stock, Peter De Bisschop, 2019, Advanced Lithography.

Constructing a robust PSCAR process for EUV

G. Vandenberghe, K. Nafus, S. Biesemans, 2018, Advanced Lithography.

Thermionic Emission as a Tool to Study Transport in Undoped nFinFETs

N. Collaert, Sunhee Lee, Gerhard Klimeck, 2010, IEEE Electron Device Letters.

GaN-on-Si: A scalable material system to realize cost effective next-generation solid state lighting and power devices

S. Decoutere, B. Dutta, S. Biesemans, 2010, 2010 Symposium on VLSI Technology.

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Lifetime-enhanced transport in silicon due to spin and valley blockade.

N. Collaert, Gerhard Klimeck, L. Hollenberg, 2010, Physical review letters.

PVD-HfSiON gate dielectrics with Ni-FUSI electrode for 65nm LSTP application

A. Veloso, M. Jurczak, S. Kubicek, 2005 .

Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

T. Schram, C. Adelmann, V. Paraschiv, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Performance and leakage optimization in carbon and fluorine co-implanted pMOSFETs

P. Absil, S. Biesemans, T. Hoffman, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Tunable Kondo effect in a single donor atom.

N. Collaert, S. Biesemans, S. Rogge, 2009, Nano letters.

Transport spectroscopy of a single dopant in a gated silicon nanowire.

N. Collaert, M. Jurczak, I. Ferain, 2006, Physical review letters.

A novel Kondo effect in single atom transistors

N. Collaert, S. Biesemans, S. Rogge, 2010, 2010 International Conference on Nanoscience and Nanotechnology.

Composition influence on the physical and electrical properties of SrxTi1-xOy-based metal-insulator-metal capacitors prepared by atomic layer deposition using TiN bottom electrodes

H. Bender, K. Opsomer, G. Pourtois, 2009 .

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

C. Vrancken, A. Veloso, S. Biesemans, 2006, IEEE Electron Device Letters.

Transient and end silicide phase formation in thin film Ni/polycrystalline-Si reactions for fully silicided gate applications

C. Detavernier, J. Kittl, J. Jordan-Sweet, 2007 .

Kinetics of Ni3Si2 formation in the Ni2Si–NiSi thin film reaction from in situ measurements

C. Detavernier, J. Kittl, J. Jordan-Sweet, 2007 .

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 International Electron Devices Meeting.

Seed Layer and Multistack Approaches to Reduce Leakage in SrTiO3-Based Metal–Insulator–Metal Capacitors Using TiN Bottom Electrode

H. Bender, K. Opsomer, C. Detavernier, 2010 .

Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices

N. Horiguchi, L. Ragnarsson, J. Mitard, 2021, International Electron Devices Meeting.

The Impact of Stacked Cap Layers on Effective Work Function With HfSiON and SiON Gate Dielectrics

S. Van Elshocht, A. Akheyar, S. Biesemans, 2008, IEEE Electron Device Letters.

Coherent transport through a double donor system in silicon

N. Collaert, S. Biesemans, S. Rogge, 2009, 0912.2196.

Strain Enhanced nMOS Using In Situ Doped Embedded $\hbox{Si}_{1 - x}\hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

H. Bender, S. Biesemans, D. Shamiryan, 2008, IEEE Electron Device Letters.

Interface Trap Density Metrology from Sub-Threshold Transport in Highly Scaled Undoped Si n-FinFETs

Gerhard Klimeck, Serge Biesemans, Sven Rogge, 2011, 1102.0140.

Innovative characterization techniques for ultra-scaled FinFETs

N. Collaert, Gerhard Klimeck, R. Rahman, 2010, 10th IEEE International Conference on Nanotechnology.

Sub-threshold study of undoped trigate nFinFET

N. Collaert, Sunhee Lee, Gerhard Klimeck, 2010 .

Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer

A. Veloso, C. Adelmann, A. Lauwers, 2007, IEEE Electron Device Letters.

Direct evidence of linewidth effect: Ni31Si12 and Ni3Si formation on 25nm Ni fully silicided gates

J. Kittl, A. Lauwers, S. Kubicek, 2007 .

Work function of Ni3Si2 on HfSixOy and SiO2 and its implication for Ni fully silicided gate applications

A. Veloso, J. Kittl, B. O’Sullivan, 2007 .

Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates

O. Richard, A. Veloso, M. Jurczak, 2006 .

Modulation of the effective work function of fully-silicided (FUSI) gate stacks

A. Veloso, G. Pourtois, J. Kittl, 2007 .

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON

A. Veloso, J. Kittl, A. Lauwers, 2006, IEEE Electron Device Letters.

Linewidth effect and phase control in Ni fully silicided gates

A. Veloso, J. Kittl, A. Lauwers, 2006, IEEE Electron Device Letters.

Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

A. Veloso, J. Kittl, A. Lauwers, 2008, IEEE Electron Device Letters.

Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

A. Veloso, M. Jurczak, J. Kittl, 2008, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $\hbox{Dy}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

A. Veloso, G. Pourtois, M. Jurczak, 2007, IEEE Electron Device Letters.

Achieving low V T Ni-FUSI CMOS via lanthanide incorporation in the gate stack

A. Veloso, M. Jurczak, J. Kittl, 2007 .

Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

M. Jurczak, J. Kittl, V. Paraschiv, 2007, 2007 IEEE Symposium on VLSI Technology.

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

T. Chiarella, C. Vrancken, A. Veloso, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs

K. Devriendt, A. Veloso, M. Jurczak, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

E. Augendre, A. Veloso, S. Biesemans, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Widening of FUSI RTP Process Window by Spike Anneal

J. Kittl, A. Lauwers, S. Kubicek, 2007, 2007 15th International Conference on Advanced Thermal Processing of Semiconductors.

Multi-gate devices for the 32 nm technology node and beyond

Rita Rooyackers, Nadine Collaert, Isabelle Ferain, 2008 .

Multi-gate devices for the 32nm technology node and beyond

R. Rooyackers, A. Mercha, L. Witters, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

M. Jurczak, J. Kittl, A. Lauwers, 2006, IEEE Transactions on Electron Devices.

Use of Indium and Gallium as P-Type Dopants in Si 0.1 µm MOSFETs

S. Biesemans, Stefan Kubicek Stefan Kubicek, Kristin De Meyer Kristin De Meyer, 1995 .

Transistor threshold voltage modulation by Dy2O3 rare-earth oxide capping: The role of bulk dielectrics charge

C. Adelmann, A. Lauwers, M. Aoulaiche, 2008 .

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

A. Veloso, M. Jurczak, A. Lauwers, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Positive and negative bias temperature instability in La2O3 and Al2O3 capped high-k MOSFETs

R. Degraeve, B. Kaczer, A. Akheyar, 2009, 2009 IEEE International Reliability Physics Symposium.

Reliability study of La2O3 capped HfSiON high-permittivity n-type metal-oxide-semiconductor field-effect transistor devices with tantalum-rich electrodes

T. Schram, G. Pourtois, B. O’Sullivan, 2008 .

Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors

Anabela Veloso, Olivier Richard, I. Debusschere, 2007, Microelectron. Reliab..

Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

E. Beyne, N. Horiguchi, I. Radu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

R. Rooyackers, B. Kaczer, S. Locorotondo, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Low VT metal-gate/high-k nMOSFETs — PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions

C. Adelmann, L. Ragnarsson, B. Kaczer, 2008, 2008 Symposium on VLSI Technology.

Effects of $\hbox{Al}_{2}\hbox{O}_{3}$ Dielectric Cap and Nitridation on Device Performance, Scalability, and Reliability for Advanced High- $\kappa$/Metal Gate pMOSFET Applications

T. Schram, V. Chang, L. Ragnarsson, 2007, IEEE Transactions on Electron Devices.

Single-electron effects in heavily doped polycrystalline silicon nanowires

Serge Biesemans, Zahid A. K. Durrani, Haroon Ahmed, 1998 .

Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

N. Collaert, M. Jurczak, I. Ferain, 2006, cond-mat/0603430.

Prospect of Hf-Based Gate Dielectric by PVD with FUSI Gate for LSTP Application

A. Lauwers, S. Kubicek, M. Heyns, 2006 .

45nm LSTP FET with FUSI Gate on PVD-HfO2 with excellent drivability by advanced PDA treatment

A. Veloso, M. Jurczak, S. Kubicek, 2005 .

PVD-HIGH-K GATE DIELECTRICS WITH FUSI GATE AND INFLUENCE OF PDA TREATMENT ON ON-STATE DRIVE CURRENT

Serge Biesemans, Shigenori Hayashi, S. Kubicek, 2006 .

Buried Power Rail Metal exploration towards the 1 nm Node

H. Mertens, K. Devriendt, J. Geypen, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Buried power rail integration for CMOS scaling beyond the 3 nm node

H. Mertens, Z. Tao, G. Mannaert, 2022, Advanced Lithography.

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

H. Mertens, Z. Tao, K. Devriendt, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

D. Tsvetanova, N. Horiguchi, J. Ryckaert, 2022, International Electron Devices Meeting.

A systematic study of trade-offs in engineering a locally strained pMOSFET

R. Rooyackers, I. De Wolf, F. Nouri, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Integration of a Stacked Contact MOL for Monolithic CFET

O. Richard, N. Horiguchi, K. Vandersmissen, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

R. Rooyackers, N. Collaert, S. Biesemans, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

T. Schram, J. Swerts, V. Chang, 2007, IEEE Electron Device Letters.

Quantification of metal oxide semiconductor field effect transistor device reliability with low-Vt lanthanum-incorporated high permittivity dielectrics

T. Schram, R. Degraeve, B. O’Sullivan, 2009 .

Analytical Calculation of Subthreshold Slope Increase in Short-Channel MOSFET's by Taking Drift Component into Account

S. Biesemans, Kristin De Meyer Kristin De Meyer, 1995 .

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

G. Pourtois, M. Jurczak, H. Yu, 2006, IEEE Electron Device Letters.

Transport-based dopant metrology in advanced FinFETs

N. Collaert, S. Biesemans, G. Klimeck, 2008, 2008 IEEE International Electron Devices Meeting.

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Liesbeth Witters, Serge Biesemans, Stefan Kubicek, 2010 .

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

S. Van Elshocht, P. Lehnen, C. Vrancken, 2007, 2007 IEEE Symposium on VLSI Technology.

Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

H. Tigelaar, T. Chiarella, J. Ramos, 2006, 2006 International Electron Devices Meeting.

Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI

A. Veloso, M. Jurczak, J. Kittl, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

S. Locorotondo, T. Chiarella, C. Vrancken, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

R. Dittrich, L. Ragnarsson, B. Parvais, 2009, 2009 Proceedings of ESSCIRC.

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

B. Parvais, R. Rooyackers, A. Mercha, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

R. Rooyackers, E. Augendre, N. Collaert, 2006, 2006 International Electron Devices Meeting.

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

R. Rooyackers, T. Skotnicki, N. Collaert, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

R. Rooyackers, N. Collaert, G. Eneman, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..