J. Draper

发表

The architecture of the DIVA processing-in-memory chip

Chun Chen, Jeff LaCoss, John J. Granacki, 2002, ICS '02.

Achieving On-chip Fault-tolerance Utilizing BIST Resources

J. Draper, 2006 .

Floating-point division and square root using a Taylor-series expansion algorithm

J. Draper, Taek-Jun Kwon, J. Sondeen, 2007 .

8.0 Conclusions and Future Work

J. Chame, V. Freeh, P. Kogge, 1999 .

Squaring units and a comparison with multipliers

Aditya M. Deshpande, J. Draper, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture

Jeff LaCoss, John J. Granacki, William C. Athas, 1999, ACM/IEEE SC 1999 Conference (SC'99).

Fully Printed All-Solid-State Organic Flexible Artificial Synapse for Neuromorphic Computing.

Chongwu Zhou, J. Draper, Xuan Cao, 2019, ACS applied materials & interfaces.

Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks

Ji Li, Qinru Qiu, Yanzhi Wang, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Single-event transient mitigation in sub-micron combinational circuits

Mahta Haghi, J. Draper, Jeff Draper, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

A single-event upset hardening technique for high speed MOS Current Mode Logic

Jeffrey T. Draper, Mahta Haghi, J. Draper, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

The 90 nm Double-DICE storage element to reduce Single-Event upsets

Mahta Haghi, Jeff Draper, J. Draper, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Jeffrey T. Draper, Sandeepan DasGupta, Riaz Naseer, 2007, GLSVLSI '07.

Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology

Rashed Zafar Bhatti, Riaz Naseer, Jeff Draper, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

DF-DICE: a scalable solution for soft error tolerant circuit design

Jeffrey T. Draper, Riaz Naseer, J. Draper, 2006, 2006 IEEE International Symposium on Circuits and Systems.

The DF-dice storage element for immunity to soft errors

J. Draper, R. Naseer, J. Draper, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture

Jaewook Shin, Mary W. Hall, Joonseok Park, 1999, ACM/IEEE SC 1999 Conference (SC'99).

Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs

J. Draper, R. Naseer, J. Draper, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

DEC ECC design to improve memory reliability in Sub-100nm technologies

Jeffrey T. Draper, Riaz Naseer, J. Draper, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

SINGLE-EVENT EFFECTS CHARACTERIZATION AND SOFT ERROR MITIGATION IN 90nm COMMERCIAL-DENSITY SRAMs

Jeffrey Draper, J. Sondeen, Y. Boulghassoul, 2008 .

HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks

Ji Li, Qinru Qiu, Yanzhi Wang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A bus-efficient low-latency network interface for the PDSS multicomputer

Jeffrey T. Draper, Jefferey G. Koller, Craig S. Steele, 1997, Proceedings. The Sixth IEEE International Symposium on High Performance Distributed Computing (Cat. No.97TB100183).

Standard cell based pseudo-random clock generator for statistical random sampling of digital signals

J. Draper, K.M. Chugg, R.Z. Bhatti, 2007, 2007 50th Midwest Symposium on Circuits and Systems.

The M-Cache: A Message-Handling Mechanism for Multicomputer Systems

Joydeep Ghosh, Jeffrey T. Draper, Joydeep Ghosh, 1994, Parallel Comput..

Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management

Jon C. Hiller, C. J. Holland, Benjamin C. Lee, 2012 .

Duty cycle measurement and correction using a random sampling technique

J. Draper, R.Z. Bhatti, M. Denneau, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

A.F. Witulski, L.W. Massengill, M.A. Bajura, 2007, IEEE Transactions on Nuclear Science.

Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits

Ji Li, Jeffrey T. Draper, J. Draper, 2017, ACM Trans. Design Autom. Electr. Syst..

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, 2005, J. VLSI Signal Process..

An area-efficient router for the Data-Intensive Architecture (DIVA) system

Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, 2004, 17th International Conference on VLSI Design. Proceedings..

A Comprehensive Analytical Model for Wormhole Routng in Multicomputer Systems

Joydeep Ghosh, Jeffrey T. Draper, Joydeep Ghosh, 1994, J. Parallel Distributed Comput..

The Red Rover Algorithm for Deadlock-Free Routing on Bidirectional Rings

Jeffrey T. Draper, J. Draper, 1996, PDPTA.

Performance Evaluation of a Parallel I/O Subsystem for Hypercube Multicomputers

Joydeep Ghosh, Jeffrey T. Draper, Kelvin D. Goveas, 1993, J. Parallel Distributed Comput..

Leakage energy estimates for HPC applications

Jeffrey T. Draper, Aditya M. Deshpande, J. Draper, 2013, E2SC '13.

Comparing squaring and cubing units with multipliers

J. Draper, A. Deshpande, Aditya M. Deshpande, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

A New Metric to Measure Cache Utilization for HPC Workloads

Jeffrey T. Draper, Aditya M. Deshpande, J. Draper, 2016, MEMSYS.

Modeling Data Movement in the Memory Hierarchy in HPC Systems

Jeffrey T. Draper, Aditya M. Deshpande, J. Draper, 2015, MEMSYS.

An asymmetric adaptive-precision energy-efficient 3DIC multiplier

Jeffrey T. Draper, Gopi Neela, J. Draper, 2013, ACM Great Lakes Symposium on VLSI.

Design trade-offs for load/store buffers in embedded processing environments

Young Hoon Kang, J. Draper, J. Draper, 2007, 2007 50th Midwest Symposium on Circuits and Systems.

Floating-point division and square root using a Taylor-series expansion algorithm

Jeffrey T. Draper, Taek-Jun Kwon, J. Draper, 2007, 2007 50th Midwest Symposium on Circuits and Systems.

A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability

Ravinder Singh, Jeffrey T. Draper, Jeff Sondeen, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A 0.18/spl mu/m CMOS implementation of an area efficient precise exception handling unit for processing-in-memory systems

J. Draper, S. Mediratta, J. Sondeen, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip

Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, 2002, Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors.

High performance training of deep neural networks using pipelined hardware acceleration and distributed memory

Mingxi Cheng, Ji Li, Shahin Nazarian, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

TID Damage and Annealing Response of 90 nm Commercial-Density SRAMs

J. Draper, Y. Boulghassoul, J. Sondeen, 2008 .

Effective realization of on-chip fault-tolerance utilizing BIST resources

Jeffrey Draper, S. Mediratta, J. Draper, 2006 .

On-chip Fault-tolerance Utilizing BIST Resources

J. Draper, S.D. Mediratta, J. Draper, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM

Jeffrey T. Draper, Sandeepan DasGupta, Riaz Naseer, 2007, 2007 IEEE International Symposium on Circuits and Systems.