F. Sebaai

发表

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

R. Ritzenthaler, T. Schram, N. Horiguchi, 2013 .

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

S. Chew, T. Schram, K. Devriendt, 2014 .

Replacement fin processing for III–V on Si: From FinFets to nanowires

Niamh Waldron, Nadine Collaert, Farid Sebaai, 2016 .

Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory

G. Groeseneken, S. Lavizzari, M. Pešić, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, IEEE Transactions on Electron Devices.

First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects

A. Hikavyy, H. Bender, A. Thean, 2013, 2013 Symposium on VLSI Circuits.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2021, 2021 Symposium on VLSI Technology.

Integration of Ruthenium-based Wordline in a 3-D NAND Memory Devices

M. Rosmeulen, S. Ramesh, L. Zhang, 2020, 2020 IEEE International Memory Workshop (IMW).

Dielectric reliability of 70nm pitch air-gap interconnect structures

G. Beyer, H. Bender, F. Sebaai, 2011 .

An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2018, 2018 IEEE Symposium on VLSI Technology.

(Invited) Selective Etch of Si and SiGe for Gate All-Around Device Architecture

Naoto Horiguchi, Liesbeth Witters, Aaron Thean, 2015 .

Wet Etching Behavior of Poly-Si in TMAH Solution

Farid Sebaai, Jim Snow, Hiroaki Takahashi, 2012 .

Development of a Wet Silicon Removal Process for Replacement Metal Gate and Sacrificial Fin

A. Veloso, F. Sebaai, H. Struyf, 2011 .

Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

A. Hikavyy, E. Rosseel, K. Devriendt, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG

A. Hikavyy, A. De Keersgieter, G. Mannaert, 2019, 2019 Symposium on VLSI Technology.

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, 2018 IEEE Symposium on VLSI Technology.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

S. Chew, T. Schram, K. Devriendt, 2013 .

Process control & integration options of RMG technology for aggressively scaled devices

S. Chew, T. Schram, K. Devriendt, 2012, Symposium on VLSI Technology.

W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

Tom Schram, Anabela Veloso, S. A. Chew, 2013 .

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Naoto Horiguchi, Tom Schram, Farid Sebaai, 2018 .

N5 technology node dual-damascene interconnects enabled using multi patterning

S. Decoster, J. Ryckaert, K. Croes, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

D. Mocuta, J. Mitard, F. Masuoka, 2019, 2019 Symposium on VLSI Technology.

First Demonstration of Ruthenium and Molybdenum Word lines Integrated into 40nm Pitch 3D-NAND Memory Devices

M. Rosmeulen, S. Ramesh, F. Sebaai, 2021, 2021 Symposium on VLSI Technology.

Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

Farid Sebaai, Kurt Wostyn, Frank Holsteyns, 2018, Solid State Phenomena.

Wet Selective SiGe Etch to Enable Ge Nanowire Formation

Farid Sebaai, L. Witters, Kurt Wostyn, 2016 .

Scaled, Novel Effective Workfunction Metal Gate Stacks for Advanced Low-VT, Gate-All-Around Vertically Stacked Nanosheet FETs with Reduced Vertical Distance between Sheets

H. Mertens, R. Ritzenthaler, M. Kim, 2019, Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials.

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

Niamh Waldron, Nadine Collaert, Farid Sebaai, 2014, IEEE Electron Device Letters.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

H. Mertens, R. Ritzenthaler, Z. Tao, 2020, 2020 IEEE Symposium on VLSI Technology.

A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash

M. Rosmeulen, O. Richard, S. Ramesh, 2022, IEEE Electron Device Letters.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, IEEE Transactions on Electron Devices.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 Symposium on VLSI Technology.

Buried Power Rail Metal exploration towards the 1 nm Node

H. Mertens, K. Devriendt, J. Geypen, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

E. Simoen, E. Vecchio, H. Bender, 2013, 2013 Symposium on VLSI Technology.

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

J. Ryckaert, T. Chiarella, N. Horiguchi, 2020, 2020 IEEE Symposium on VLSI Technology.

Buried power rail integration for CMOS scaling beyond the 3 nm node

H. Mertens, Z. Tao, G. Mannaert, 2022, Advanced Lithography.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

H. Mertens, Z. Tao, K. Devriendt, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Plasma etch selectivity study and material screening for self-aligned gate contact (SAGC)

Andrew Metz, Farid Sebaai, Steven Demuynck, 2019, Advanced Lithography.

Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2022, 2022 International Electron Devices Meeting (IEDM).

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections

A. Jourdain, A. Hikavyy, G. Mannaert, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Selectivity Tuning by Peroxide Concentration for the Selective Etching of SiGe20 to Si and SiGe40 to SiGe20

F. Sebaai, A. Klipp, E. Altamirano-Sanchez, 2023, Solid State Phenomena.

Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm

C. Merckling, N. Waldron, N. Collaert, 2016, 2016 IEEE Symposium on VLSI Technology.

Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies

A. Vais, N. Collaert, N. Horiguchi, 2019, Advanced Lithography.

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

A. Vais, C. Merckling, N. Waldron, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Geert Hellings, Eddy Simoen, Niamh Waldron, 2017 .

First Demonstration of SiGe Channel in Macaroni Geometry for Future 3D NAND

A. Hikavyy, F. Sebaai, E. Vecchio, 2017, 2017 IEEE International Memory Workshop (IMW).

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

H. Bender, G. Eneman, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM

Z. Tao, K. Devriendt, D. Mocuta, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes

Farid Sebaai, Lan Peng, Deniz Sabuncuoglu Tezcan, 2015 .