José Pineda de Gyvez

发表

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters

Amir Zjajo, José Pineda de Gyvez, 2008, 2008 Design, Automation and Test in Europe.

Chaotic generation of PN sequences: a VLSI implementation

José Pineda de Gyvez, A. Dornbusch, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Resistance characterization for weak open defects

Rosa Rodríguez-Montañés, José Pineda de Gyvez, Paul Volf, 2002, IEEE Design & Test of Computers.

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors

Luca Benini, Andrea Bartolini, Davide Rossi, 2017, Microprocess. Microsystems.

Testing and diagnosis of power switches in SOCs

Sandeep Kumar Goel, José Pineda de Gyvez, Maurice Meijer, 2006, Eleventh IEEE European Test Symposium (ETS'06).

Power supply ramping for quasi-static testing of PLLs

Guido Gronthoud, Thomas Burger, Martin Posch, 2004, 2004 International Conferce on Test.

Glitch-free discretely programmable clock generation on chip

José Pineda de Gyvez, Maurice Meijer, Francesco Pessolano, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Word line pulsing technique for stability fault detection in SRAM cells

Manoj Sachdev, José Pineda de Gyvez, Andrei Pavlov, 2005, IEEE International Conference on Test, 2005..

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs

Qin Tang, Amir Zjajo, Michel Berkelaar, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs

Luca Benini, Lothar Thiele, Andres Gomez, 2018, 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Power supply noise monitor for signal integrity faults

José Pineda de Gyvez, Josep Rius Vázquez, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Prelayout interconnect yield prediction

Phillip Christie, José Pineda de Gyvez, P. Christie, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Efficient testing and diagnosis of faulty power switches in SOCs

Sandeep Kumar Goel, José Pineda de Gyvez, Maurice Meijer, 2007, IET Comput. Digit. Tech..

An analytical model for interdependent setup/hold-time characterization of flip-flops

Kees G. W. Goossens, Hailong Jiao, José Pineda de Gyvez, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing

Alan Chang, Mini Jayakrishnan, Tae-Hyoung Kim, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits

José Pineda de Gyvez, Josep Rius Vázquez, Maurice Meijer, 2005, PATMOS.

Time-domain analog wavelet transform in real-time

José Pineda de Gyvez, Oscar Moreira-Tamayo, J. P. D. Gyvez, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Body bias driven design synthesis for optimum performance per area

José Pineda de Gyvez, Maurice Meijer, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Color image processing in a cellular neural-network environment

José Pineda de Gyvez, Chi-Chien Lee, J. P. D. Gyvez, 1996, IEEE Trans. Neural Networks.

Encoded-Low Swing Technique for Ultra Low Power Interconnect

Harry J. M. Veendrick, José Pineda de Gyvez, Rohini Krishnan, 2003, FPL.

Low energy FPGA interconnect design

Martijn T. Bennebroek, José Pineda de Gyvez, Rohini Krishnan, 2004, GLSVLSI '04.

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits

José Pineda de Gyvez, Josep Rius Vázquez, Maurice Meijer, 2006, J. Low Power Electron..

Evaluation of signature-based testing of RF/analog circuits

Amir Zjajo, José Pineda de Gyvez, 2005, European Test Symposium (ETS'05).

Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator

Twan Basten, Majid Nabi, Jos Huisken, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Chip Health Tracking Using Dynamic In-Situ Delay Monitoring

Kees G. W. Goossens, José Pineda de Gyvez, Hadi Ahmadi Balef, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Low energy FPGA interconnect design

Martijn T. Bennebroek, José Pineda de Gyvez, Rohini Krishnan, 2004, FPGA '04.

A universal interface between PC and neural network hardware

Edgar Sánchez-Sinencio, José Pineda de Gyvez, Apollo Q. Fong, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory

Rolf Drechsler, Chip-Hong Chang, Chulwoo Kim, 2019, IEEE Trans. Very Large Scale Integr. Syst..

Multi-VDD Testing for Analog Circuits

Guido Gronthoud, José Pineda de Gyvez, Rashid Amine, 2005, J. Electron. Test..

On the design and implementation of a wafer yield editor

Jochen A. G. Jess, José Pineda de Gyvez, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A scan-chain based state retention methodology for IoT processors operating on intermittent energy

Luca Benini, José Pineda de Gyvez, Hamed Fatemi, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Structural Fault Modeling and Fault Detection Through Neyman–Pearson Decision Criteria for Analog Integrated Circuits

Guido Gronthoud, Amir Zjajo, José Pineda de Gyvez, 2006, J. Electron. Test..

Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage

Bo Liu, José Pineda de Gyvez, Hamid Reza Pourshaghaghi, 2011, 2011 14th Euromicro Conference on Digital System Design.

Power-scan chain: design for analog testability

Amir Zjajo, José Pineda de Gyvez, Rodger Schuttert, 2005, IEEE International Conference on Test, 2005..

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

José Pineda de Gyvez, Maurice Meijer, J. P. D. Gyvez, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Digital Systems Power Management for High Performance Mixed Signal Platforms

Gerard Villar Pique, Yu Pu, Maarten Vertregt, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

Amir Zjajo, José Pineda de Gyvez, A. Zjajo, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design

Hailong Jiao, Jos Huisken, José Pineda de Gyvez, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Pre-layout prediction of interconnect manufacturability

Phillip Christie, José Pineda de Gyvez, 2001, SLIP '01.

Circuit valorization in the IC design ecosystem

Maarten Vertregt, José Pineda de Gyvez, Hamed Fatemi, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN

Marc Geilen, Jos Huisken, Min Li, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Maarten Vertregt, José Pineda de Gyvez, Ben Kup, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation

Ajay Kapoor, José Pineda de Gyvez, Maurice Meijer, 2010, J. Low Power Electron..

Technology exploration for adaptive power and frequency scaling in 90nm CMOS

José Pineda de Gyvez, Maurice Meijer, Francesco Pessolano, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Threshold voltage mismatch (/spl Delta/V/sub T/) fault modeling

Rosa Rodríguez-Montañés, José Pineda de Gyvez, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Programmable techniques for cell stability test and debug in embedded SRAMs

Manoj Sachdev, José Pineda de Gyvez, Andrei Pavlov, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Statistical noise margin estimation for sub-threshold combinational circuits

Yajun Ha, Henk Corporaal, Yu Pu, 2008, 2008 Asia and South Pacific Design Automation Conference.

Lower power by voltage stacking: A fine-grained system design approach

Ajay Kapoor, José Pineda de Gyvez, Hamed Fatemi, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

An Analog Integrated Circuit Design Laboratory

Edgar Sánchez-Sinencio, José Silva-Martínez, Antonio F. Mondragón-Torres, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Standard cell sizing for subthreshold operation

Bo Liu, Maryam Ashouei, Jos Huisken, 2012, DAC Design Automation Conference 2012.

Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling

José Pineda de Gyvez, Hamid Reza Pourshaghaghi, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Floorplan and placement methodology for improved energy reduction in stacked power-domain design

Andrew B. Kahng, Jiajia Li, Ajay Kapoor, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Sliding-Mode Control to Compensate PVT Variations in dual core systems

José Pineda de Gyvez, Hamed Fatemi, Hamid Reza Pourshaghaghi, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Supervised learning based model for predicting variability-induced timing errors

Rajesh K. Gupta, Abbas Rahimi, Balakrishnan Narayanaswamy, 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

Functional vs. multi-VDD testing of RF circuits

Guido Gronthoud, José Pineda de Gyvez, Estella Silva, 2005, IEEE International Conference on Test, 2005..

Vdd ramp testing for rf circuits

Guido Gronthoud, José Pineda de Gyvez, Rashid Amine, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Architectural Analysis for Wirelessly Powered Computing Platforms

Ajay Kapoor, José Pineda de Gyvez, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez, 2012, IEEE Transactions on Instrumentation and Measurement.

A capacitor cross-coupled common-gate low-noise amplifier

David J. Allstot, Edgar Sánchez-Sinencio, José Pineda de Gyvez, 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

Low power latch based design with smart retiming

Hailong Jiao, Jos Huisken, José Pineda de Gyvez, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Threshold voltage and power-supply tolerance of CMOS logic design families

José Pineda de Gyvez, Madhuban Kishor, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Average Leakage Current Estimation of CMOS Logic Circuits

José Pineda de Gyvez, Eric van de Wetering, 2001, VTS.

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers

Yanxiang Huang, Ajay Kapoor, José Pineda de Gyvez, 2015, Microprocess. Microsystems.

Vt balancing and device sizing towards high yield of sub-threshold static logic gates

Yajun Ha, Henk Corporaal, Yu Pu, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths

Kees G. W. Goossens, José Pineda de Gyvez, Hamed Fatemi, 2018, ACM Great Lakes Symposium on VLSI.

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation

José Pineda de Gyvez, Sebastian M. Londono, 2012, 2012 IEEE International SOC Conference.

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors

Luca Benini, Andrea Bartolini, Davide Rossi, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply

Yajun Ha, Henk Corporaal, Yu Pu, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A microcontroller with 96% power-conversion efficiency using stacked voltage domains

Kofi A. A. Makinwa, Arjun Majumdar, Ajay Kapoor, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

Full-signature real-time corrosion detection of underground casing pipes

Jiming Yin, Mi Lu, José Pineda de Gyvez, 2000, IEEE Trans. Instrum. Meas..

A power supply ramping and current measurement based technique for analog fault diagnosis

Edgar Sánchez-Sinencio, José Pineda de Gyvez, Shyam S. Somayajula, 1994, Proceedings of IEEE VLSI Test Symposium.

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage

Yajun Ha, Henk Corporaal, Yu Pu, 2010, IEEE Journal of Solid-State Circuits.

Real-time wavelet-integrated corrosion detection system for casing pipes

Jiming Yin, Mi Lu, José Pineda de Gyvez, 2000, Integr. Comput. Aided Eng..

Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking

José Pineda de Gyvez, Hamid Reza Pourshaghaghi, H. Pourshaghaghi, 2013, IEEE Transactions on Computers.

Low energy switch block for FPGAs

José Pineda de Gyvez, Rohini Krishnan, J. P. D. Gyvez, 2004, 17th International Conference on VLSI Design. Proceedings..

Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm

Amir Zjajo, José Pineda de Gyvez, Shaji Krishnan, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Standard cell library tuning for variability tolerant designs

Maarten Vertregt, José Pineda de Gyvez, Juan Diego Echeverri, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Subband coding and image compression using CNN

José Pineda de Gyvez, Oscar Moreira-Tamayo, J. P. D. Gyvez, 1999, International journal of circuit theory and applications.

Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing

José Pineda de Gyvez, Apollo Q. Fong, Ajay Kanji, 1996, Real Time Imaging.

Limits to performance spread tuning using adaptive voltage and body biasing

José Pineda de Gyvez, Maurice Meijer, Francesco Pessolano, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Yield modeling and BEOL fundamentals

José Pineda de Gyvez, J. P. D. Gyvez, 2001, SLIP '01.

Single-layer CNN simulator

José Pineda de Gyvez, Chi-Chien Lee, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Built-in current sensor for /spl Delta/I/sub DDQ/ testing of deep submicron digital CMOS ICs

José Pineda de Gyvez, Josep Rius Vázquez, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Nonlinear Computability Based on Chaos

Gabriele Manganaro, José Pineda de Gyvez, G. Manganaro, 2000, Int. J. Bifurc. Chaos.

Process-variability aware delay fault testing of /spl Delta/V/sub T/ and weak-open defects

Guido Gronthoud, Rosa Rodríguez-Montañés, José Pineda de Gyvez, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers

Yanxiang Huang, Ajay Kapoor, José Pineda de Gyvez, 2013, 2013 NORCHIP.

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters

Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez, 2012, J. Low Power Electron..

Calibration and Debugging of Multi-step Analog to Digital Converters

Amir Zjajo, José Pineda de Gyvez, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

PRESS/HOLD/RELEASE Ultrasonic Gestures and Low Complexity Recognition Based on TCN

Min Li, José Pineda de Gyvez, Emad A. Ibrahim, 2019, 2019 IEEE International Workshop on Signal Processing Systems (SiPS).

Reconfigurable Support Vector Machine Classifier with Approximate Computing

Lei Wang, Hailong Jiao, Jos Huisken, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver

Twan Basten, Majid Nabi, Hailong Jiao, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Sub-threshold custom standard cell library validation

Bo Liu, Maryam Ashouei, José Pineda de Gyvez, 2014, Fifteenth International Symposium on Quality Electronic Design.

On-chip digital power supply control for system-on-chip applications

José Pineda de Gyvez, Maurice Meijer, Ralph Otten, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits

Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

An SRAM weak cell fault model and a DFT technique with a programmable detection threshold

Manoj Sachdev, José Pineda de Gyvez, Andrei Pavlov, 2004, 2004 International Conferce on Test.

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller

José Pineda de Gyvez, Hamid Reza Pourshaghaghi, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test

Amir Zjajo, José Pineda de Gyvez, A. Zjajo, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling

Yu Pu, José Pineda de Gyvez, Maurice Meijer, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Time multiplexed color image processing based on a CNN with cell-state outputs

Lei Wang, Edgar Sánchez-Sinencio, José Pineda de Gyvez, 1998, IEEE Trans. Very Large Scale Integr. Syst..

A layout defect-sensitivity extractor

Jochen A. G. Jess, José Pineda de Gyvez, J. Jess, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

CMOS cryptosystem using a Lorenz chaotic oscillator

Edgar Sánchez-Sinencio, José Pineda de Gyvez, Gunhee Han, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

An Improved Methodology for Resilient Design Implementation

Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, 2015, ACM Trans. Design Autom. Electr. Syst..

Behavioral testing of cellular neural networks

José Pineda de Gyvez, John Willis, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Preprocessing operators for image compression using cellular neural networks

José Pineda de Gyvez, Oscar Moreira-Tamayo, J. P. D. Gyvez, 1996, ICNN.

A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT

Pieter Harpe, Shima Sedighiani, José Pineda de Gyvez, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).