M. Bednara

FPGA designs of parallel high performance GF(2233) multipliers

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2003, ISCAS.

Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration

Jürgen Teich, Ali Ahmadinia, Marcus Bednara, 2004, IEEE International Parallel and Distributed Processing Symposium.

Real time polarization sensor image processing on an embedded FPGA/multi-core DSP system

Marcus Bednara, Katarzyna Chuchacz-Kowalczyk, M. Bednara, 2015, Europe Optics + Optoelectronics.

A high performance VLIW processor for finite field arithmetic

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Reconfigurable implementation of elliptic curve crypto algorithms

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

FPGA designs of parallel high performance GF(2/sup 233/) multipliers [cryptographic applications]

J. Teich, M. Bednara, J. Gathen, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Tradeoff analysis of FPGA based elliptic curve cryptography

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Interface Synthesis for FPGA Based VLSI Processor Arrays

M. Bednara, M. Bednara, 2002 .