J. West

Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

J. West, Y. S. Choi, C. Vartuli, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A Novel TiSi/sub 2/TiN Clad Local Interconnect Technology

S. Jeng, J. West, D. Wyke, 1993, Symposium 1993 on VLSI Technology.

FSG process development for copper/damascene technology

J. D. Luttmer, T. Bonifield, J. West, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).